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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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What is the minimum instruction set required for any Assembly language to be considered useful?

I am studying Assembly programming in general, so I've decided to try and implement a "virtual microprocessor" in software, which has registers, flags and RAM to work with, implemented with variables and arrays. But since I want to simulate only the…
Fernando Aires Castello
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RISC-V: Immediate Encoding Variants

In the RISC-V Instruction Set Manual, User-Level ISA, I couldn't understand section 2.3 Immediate Encoding Variants page 11. There is four types of instruction formats R, I, S, and U, then there is a variants of S and U types which are SB and UJ…
Ammar Kurd
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Why can an executable run on both Intel and AMD processors?

How is it that an executable can work on both AMD and Intel systems? Aren't AMD's and Intel's instruction sets different? How does the executable work on both? How exactly do they compile the files to work like that? And what exactly is the role of…
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Purpose of cmove instruction in x86 assembly?

When disassembling an executable I encountered the cmove instruction. I've already searched on the Internet but I've only found that it's a conditional move, and if the source and destination are equal a mov occurs. What I don't understand yet is…
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How does one do integer (signed or unsigned) division on ARM?

I'm working on Cortex-A8 and Cortex-A9 in particular. I know that some architectures don't come with integer division, but what is the best way to do it other than convert to float, divide, convert to integer? Or is that indeed the best…
Phonon
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Are ARM instructuons SWI and SVC exactly same thing?

ARM assembly has SWI and SVC instructions for entering into 'supervisor mode'. What confuses me is, why there are two of them? Here it is said that SVC was formerly SWI. Does it mean that basically they changed the mnemonic? Are they the same thing?…
Hayri Uğur Koltuk
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itte in arm assembly

What does the following line do in arm assembly: 000031e6 2916 cmp r1, #22 000031e8 bf1a itte ne I get the first line (comparing r1 to 22) but what about the second line (I've never seen the itte command before and googling…
Johnathon
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How do applications determine if instruction set is available and use it in case it is?

Just interesting how it works in games and other software. More precisely, I'm asking for a solution in C++. Something like: if AMX available -> Use AMX version of the math library else if AVX-512 available -> Use AVX-512 version of the math…
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Why IA32 does not allow memory to memory mov?

In Intel architecture IA32, instructions like movl, movw does not allow operands that are both memory locations. For example, instruction movl (%eax), (%edx) is not permitted. Why?
Strin
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Difference between PREFETCH and PREFETCHNTA instructions

The PREFETCHNTA instruction is basically used to bring the data from main memory to caches by the prefetcher, but instructions with the NT suffix are known to skip caches and avoid cache pollution. So what does PREFETCHNTA do which is different from…
Abhishek Nikam
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Real-world analog to TIS-100

The recent game TIS-100 is centered around a rather interesting machine architecture, where the CPU consists of "nodes" which can communicate to their adjacent neighbours. I unfortunately cannot find an official link to the reference manual for…
Matthew Sainsbury
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x86 CMP Instruction Difference

Question What is the (non-trivial) difference between the following two x86 instructions? 39 /r CMP r/m32,r32 Compare r32 with r/m32 3B /r CMP r32,r/m32 Compare r/m32 with r32 Background I'm building a Java assembler, which will be used…
Pindatjuh
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Why doesn't there exists a subi opcode for MIPS?

I am very new to Assembly language. I was reading about MIPS architecture and came to know that you have addi opcode but there is no subi opcode. Why don't we have a subi opcode?
user379888
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Why are RISC-V S-B and U-J instruction types encoded in this way?

I am reading a book "Computer Organization and Design RISC-V Edition", and I came across the encoding for S-B and U-J instruction types. Those types I have mentioned above has strange encoded immediate field. S-B types separate the immediate field…
jwkoo
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What's the point of the VPERMILPS instruction (_mm_permute_ps)?

The AVX instruction set introduced VPERMILPS which seems to be a simplified version of SHUFPS (for the case where both input registers are the same). For example, the following instruction: c5 f0 c6 c1 00 vshufps xmm0,xmm1,xmm1,0x0 can be…
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