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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Am I allowed to use two registers in a MIPS addressing mode, as an index?

I have the following C row code: B[x] = A[x+7] + A[x+2]; Assuming that A is stored in $s0, B in $s1 and x in $t0. I have got the following MIPS code: add $t1, $t0, 7 add $t2, $t0, 2 lw $t3, $t1($s0) lw $t4, $t2($s0) add $t3, $t3, $t4 sw …
Ardit Shala
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What is the essence of booth's algorithm?

can anyone explain the essence of booths algorithm and how to use it in machine language?
blackem boy
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Accessing the memory with different access sizes

I am currently working on a project, where i inject bitflips (0 -> 1, or 1 -> 0) in memory or registers. Now i have to think about some special cases. Here is my question: Can there be cases, where there is a memory access on a certain memory…
AndiYo
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conditional data transfers VS n conditional control transfers(using conditional mov) in Assembly

Hi I was reading a textbook that compare conditional data transfers and conditional control transfers in assembly: above is the gotodiff (conditional jump) below is the cmovdiff (conditional mov) I don't know why v = test-expr ? then-expr :…
user9623401
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mapping from (Assembly) instruction sequences to C code

There is one exercise from my textbook: int comp(data_t a, data_t b) { return a COMP b; } shows a general comparison between arguments a and b, where we can set the data type of the arguments by declaring data_t with a typedef declaration,…
user9623401
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Need for -xarch=XXX when an instruction is used in byte code form?

I have a x86 RDRAND implementation like below. I have a similar implementation for RDSEED. inline void RDRAND32(void* output) { #if defined(HAVE_GCC_RDRAND_ASM) __asm__ ( "1:\n" ".byte 0x0f, 0xc7, 0xf0;\n" "jnc…
jww
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Assembly copying from one array to another

and sorry for the title, i couldn't imagine a way to express this in english. So i'm writing a little game in assembly for a course, and, inside of two for loops, i copy the pixel data from the "bomb" vector of pixels, to the "area" vector of…
Adrian
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Privileged instructions in Intel x86-64

I need to identify the set of all the privileged instructions in x86_64 architecture. I know some of them such as cli for clearing interrupts, but when searching in the net for a whole list, I can not find something useful even in the official Intel…
Oualid
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How RISC-V Word Operation is performed?

In case of 64-bit processor,if word operation is to be performed then will the 32nd bit will be considered as signed bit or as a magnitude bit?
ayush srivastava
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U-Boot How to run a standalone binary program?

I have compiled a simple binary file (hello.bin) and stored it on a memory card. I am running a NXP Sabre dev kit with i.mx 6 quad processor. I have started up U-boot and am trying to access the binary file and make it run. The hello.bin is…
Mattis Asp
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How are ``getfield`` instructions resolved?

Alright so I have an instance of Foo that has an Object field obj, say, and a bunch of other fields. I now create a class Bar and give it all the fields that Foo has and a few extra. In particular, Bar has obj as well. I instrument my classes to…
User1291
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Why nasm and yasm yield 67 opcode for mov r16, word [r64 - 3] instruction?

In x86-64 assembly I have following instruction mov dx, word [esi-5] Nasm 2.13.03 generates: 66 67 8B 56 FB yasm 1.3.0 generates: 67 66 8B 56 FB The 66 67 opcodes are modifiers so 8B 56 FB on its own is: mov edx, dword [rsi-5] I…
Kamil.S
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how do you work out how many bits are needed for the opcode?

There is 16 bits/word, and the instruction set consists of 17 different operations. I know that there is 5 bits needed for the opcode, but I have no idea why. Why is 5 bits needed for the opcode?
user9531960
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Simple Header Library in C / C++ for Detection of CPU Features (Supported Instruction Set)

I'd like to create a simple function for CPU features detection. I need it for Run Time dispatching of code paths by the CPU features. I'd like something really simple like: hasSSE3(), hasSSE4(), hasAVX(), hasAVX2(), etc.. It has to be portable,…
Royi
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What is the instruction format/length of this accumulator machine, given some details?

I need to learn about accumulator machines, but there is next to nothing written about them. Computer architecture channels seem to be flooded with general-purpose register ISAs (like MIPS, x86, etc). I know that accumulator machines only have one…
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