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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Creating new instruction (double operand)

I've been reading a book and i got stuck in this: They showed me this chart: I put this values by myself (does it make sense to you?): PC (program counter) = 16 bits TAR (temporary address register) = 16 bits MAR (memory address register) = 16…
user8007135
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What instructions can modern CPUs execute?

I tried searching for instruction sets of modern CPUs and did not find an answer to the question. I am interested in how modern computers compare to abstractions such as Turing machines (and showing them equivalent), so this is naturally the first…
Tony
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Pro and Cons of ISA Extensions on RISC-V cores

Because RISC-V is an open-source architecture, one can come up with ISA extensions for dedicated purposes (e.g. bit manipulation, or cryptographic implementations). While I understand that such extensions allow to speed up the calculations for a…
Raoul722
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x86-64 instruction set, AT&T syntax, confusion regarding lea and brackets

I’ve been told that lea %rax, %rdx is invalid syntax as the source needs to be in brackets, i.e lea (%rax), %rdx I think I’ve clearly misunderstood both lea and the purpose of brackets. I thought that lea %rax, %rdx would move the memory…
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Can address be negative in the immediate field of the RISC-V I-Type?

I learned that 'subi' isn't needed in RICS_V ISA and the immediate field represents a two's complement integer to do the operation altogether. My question is, if the immediate part can be represented as a negative number then could we also represent…
Johntopia
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Trying to understand how jump instruction calculate the address when different Program counter present

Currently I am understanding a RISC-V(ISA) instruction set architecture with three extensions I, M, and C extension. Almost I have understood all the instructions of I, M, and C extension but I haven't found yet that how jumps and branches…
Ali Hassan Ahmed Khan
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Get system architecture(x86-x64) via assembly on Windows

Is there any “global” code that can runs under both x86 and x64 architectures and determines the system architecture?(in assembly language) etc : in some operating system bootable setups the launcher can runs under both architectures I want…
someone
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Clock Cycles for the invlpg instruction

I was reading some documentation about the invlpg instruction for Intel Pentium processors and it says that it takes 25 clock cycles. I thought that this depended on the implementation (the particular CPU) and not the actual instruction set…
Kevin Tan
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How many values can be stored per physical address in Memory?

I've read that you can only store one value per physical address in Ram. Now this data could be an instruction or data. Is this due to when the CPU reads in a Word from Ram, it can only deal with one value at a time? be that an instruction, int or a…
Rob
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How CPU predicts, the instruction and data limits in the sequence of binary information of binary file?

How CPU Differentiate the instruction from the data? How CPUs determines the length of instruction(it varies from 1 byte upto 15 byte max) while executing the code? if suppose the cpu does not determine the length of instruction, it may take the…
Vintage Coder
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extract useful information from xml files . These xml files are used by the manufacturer to update the MCU?

I'm new to reverse engineering and embedded micro-controllers in general and I want to find useful information about my MCU's firmware: They use XML files to update the MCU. Can I do a hex-dump on the following file? VP002.XML Programming…
Peter Wilner
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Getting supported CPU Features/Instructions in Java

I have a Java application that is a wrapper for a different application (which requires >=SSE4_1 to be supported). Because of this, I want to be able to detect the avaible CPU Features (Instruction Sets) in my Java application. I have not yet found…
Mining_Pickaxe
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Why VS C/C++ AVX512 compiled software work on my system while my CPU has no AVX512?

I have seen recently that Visual Studio 2019 Preview has added an option to compile with AVX512. OK, I tried it and it worked. But why does it work while my CPU has no such capability? I am using the following C/C++ script to detect the CPU…
Hattrick HKS
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Preventing unaligned accesses at the instruction set level

Are there instruction sets in which unaligned accesses are prevented by using non-byte addresses? As far as I know, most architectures use byte addresses everywhere, but penalize or throw exceptions for unaligned accesses. Wouldn't it make sense to…
anol
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Why does MIPS use one delay slot instead of two?

This seems to be the case in many RISC architectures. Since filling one delay slot saves us 50% of otherwise wasted cycles, why not give the programmer a chance to use both slots?
abjoshi - Reinstate Monica
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