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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Why does the FMA _mm256_fmadd_pd() intrinsic have 3 asm mnemonics, "vfmadd132pd", "231" and "213"?

Could someone explain to me why there are 3 variants of the fused multiply-accumulate instruction: vfmadd132pd, vfmadd231pd and vfmadd213pd, while there is only one C intrinsics _mm256_fmadd_pd? To make things simple, what is the difference between…
Zheyuan Li
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Easiest/Best Way to Learn the x86 Instruction Set?

I would like to learn the x86 Instruction Set Architecture. I don't meaning learning an assembly for x86. I want to understand the machine code baby. The reason is that I would like to write an assembler for x86. Then I want to write a compiler that…
mudgen
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Why are CISC processors harder to pipeline? In what sense are some instructions "more complex" than others?

According to "Computer Architecture and Organization" by Miles Murdoca and Vincent Heuring, CISC instructions do not fit pipelined architectures very well. For pipelining to work effectively, each instruction needs to have similarities to…
Celeritas
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where can I find a description of *all* MIPS instructions

Does anyone know of a web site where I can find a list of 32-bit MIPS instructions/opcodes, with the following features: Clearly distinguishes between real opcodes and assembly-language macros (pseudo-instructions) Describes the instruction…
Dan Lenski
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Disabling AVX2 in CPU for testing purposes

I've got an application that requires AVX2 to work correctly. A check was implemented to check during application start if CPU has AVX2 instruction. I would like to check if it works correctly, but i only have CPU that has AVX2. Is there a way to…
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How does the CPU distinguish 'CALL rel16' (E8 cw) and 'CALL rel32' (E8 cd)?

How does the CPU distinguish CALL rel16 (E8 cw) and CALL rel32 (E8 cd)? According to this site, mirroring the Intel architecture manuals, the opcodes for CALL rel16 and CALL rel32 are E8 cw and E8 cd, respectively. This has made me wonder, how does…
Shuzheng
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How does mtune actually work?

There's this related question: GCC: how is march different from mtune? However, the existing answers don't go much further than the GCC manual itself. At most, we get: If you use -mtune, then the compiler will generate code that works on any of…
Marc.2377
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CS:APP example uses idivq with two operands?

I am reading about x86-64 (and assembly in general) through the book "computer systems a programmer's perspective"(3rd edition). The author, in compliance with other sources from the web, states that idivq takes one operand only - just as this one…
That Guy
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How does the CPU know its instruction set?

Basic computer operation question but I'm not sure how to ask it. When we say that a computer has an instruction set, how does the computer know what that set is? Is it stored in a ROM chip? Is it stored in the CPU somewhere? Where did the…
johnny
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What EXACTLY is the difference between intel's and amd's ISA, if any?

I know people have asked similar questions like this before, however there is so much conflicting information that I really want to try and clear it up once and for all. I will attempt to do so by clearly distinguishing between instruction set…
Jason
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What is an assembly-level representation of pushl/popl %esp?

I'm trying to understand the behavior of pushing and popping the stack pointer register. In AT&T: pushl %esp and popl %esp Note that they store the computed value back into %esp. I'm considering these instructions independently, not in sequence.…
amorimluc
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MWAIT vs HALT in terms of efficiency

I'm raising a wonder in regards to MONITOR-MWAIT vs HLT instructions. Both halts the processor, both wakes up on various external triggers (interrupts etc). In my experiments, HLT and MWAIT function almost the same, when taking in account : If…
win32 devPart
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x86 Program Counter abstracted from microarchitecture?

I'm reading the book The RISC-V Reader: An Open Architecture Atlas. The authors, to explain the isolation of an ISA (Instruction Set Architecture) from a particular implementation (i.e., microarchitecture) wrote: The temptation for an architect is…
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Are PUSH/POP instructions considered RISC or CISC?

I was asked in an interview if PUSH and POP are RISC or CISC instructions. I said that they were RISC, but they told me that they were actually CISC instructions. I suggested that ARM (a common RISC implementation) has these instructions, but they…
user1998844
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How is machine code stored in the EXE file?

My questions are as follows: How does the Portable Executable format (on Windows/Unix) relate to the x86/x64 instruction set in general? Does the PE format store the exact set of opcodes supported by the processor, or is it a more generic format…
Robin Rodricks
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