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I am new to vhdl and FPGA. For my project I need to use for loop. When I simulate my code it keeps counting and not stopping. I want my code to execute only once, my point is when the loop reaches it's limit code will stop executing. Here is my code.

process(clk)
begin
        
        report "Hello";
      
        for j in 0 to 3 loop 
            if (j<4) then
              cA <= cA + 1;
              report "middle";
              exit;

            end if;
        end loop;  
        
        report "done";
      
 end process;
radium88
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  • j is always less than 4, no need to evaluate it. It's not clear why you report "middle" 4 times. Synthesizing a counter with a latch (the evaluation of clk is not confined to one clock edge) results in a gated oscillator, an increment by 1 is guaranteed to invert as least one binary element so you have feedback and inversion. Without cA in the sensitivity list behavioral simulation won't match post synthesis. The type of cA isn't known from your process statement. – user16145658 Dec 09 '21 at 17:41

1 Answers1

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As probably explained in your textbook, a VHDL process is an infinite loop. After the last instruction has been executed, the first one executes.

A process with sensitivity list (clk in your case) is equivalent to the same process without sensitivity list but with a final wait statement on the list. Your process is thus equivalent to:

process
begin    
  report "Hello";
  for j in 0 to 3 loop 
    if (j<4) then
      cA <= cA + 1;
      report "middle";
      exit;
    end if;
  end loop;  
  report "done";
  wait on clk;
end process;

So, your loop executes a first time at the very beginning of the simulation and the process suspends, waiting for a clk change. It resumes each time clk changes, executes the loop again, and suspends. If your clock never stops, your process will always be resumed twice a clock period (once on the rising edge and once on the falling edge).

If you want to execute this loop only once at the very beginning of the simulation, remove the sensitivity list and add wait as last statement. A simple wait means "wait forever". It suspends the process definitely:

process
begin    
  report "Hello";
  for j in 0 to 3 loop 
    if (j<4) then
      cA <= cA + 1;
      report "middle";
      exit;
    end if;
  end loop;  
  report "done";
  wait;
end process;

If, instead, you want to execute the loop and stop only after a particular event happened, say a rising edge of the clock where signal go is asserted high, add another wait statement at the beginning of the process:

process
begin
  wait until rising_edge(clk) and go = '1';
  report "Hello";
  for j in 0 to 3 loop 
    if (j<4) then
      cA <= cA + 1;
      report "middle";
      exit;
    end if;
  end loop;  
  report "done";
  wait;
end process;
Renaud Pacalet
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  • Dear, Mr Pacalet. Thanks a lot for your help. Your solution solved my problem. I would like to point out another problem, which I am facing right now. In my program I have to implement a math function, where I have to calculate the value in decimals. I have used real data type but this is not synthesizable. Is there any way I can implement the decimals points in my VHDL code, which is also synthesizable? This question is not related to original question. I am sorry for the trouble. Thanks. – radium88 Dec 10 '21 at 21:42
  • Glad it helped. You do not give enough information about your other problem. Depending on the math function, on the range of your numbers, on the accuracy you need, on your hardware target, the answers can vary a lot, from fixed point calculations to floating point units, CORDIC... I suggest to 1) search SO for similar questions, and 2) if you do not find what you need, ask a new question with all the details. – Renaud Pacalet Dec 11 '21 at 08:00