0

I made a simple counter that goes to 32 and a testbench for it. I'm not sure why the value for the output (co) is still coming out as StX. I've been trying to debug this for many hours now and I'm not sure of the issue.

Verilog code

Simulation

toolic
  • 57,801
  • 17
  • 75
  • 117

2 Answers2

1

co is X (unknown) because it is a continuous assignment to an expression dependent on current, which is X. current is X because you declared it as a reg, and reg types default to X at time 0, and then you never assign it to a known value.

Your testbench always drives rst as 0. This means line 8 is never executed. Line 10 will be executed at every rising clk edge, but current will remain at X. X+1 returns X.

You need to reset your design properly. At time 0, you should assert the reset by setting rst=1. After a delay, you should release the reset setting rst=0.

initial begin
    clk = 0;
    rst = 1; // Assert reset

    #20;
    rst = 0; // Release reset

    #10;
    en = 1;
    init = 1;
end
toolic
  • 57,801
  • 17
  • 75
  • 117
0

The reset of you counter is active high. You never set it to 1. You need to set it to 1 for at least one clock cycle.

dave_59
  • 39,096
  • 3
  • 24
  • 63