VHDL Modelsim: Array lengths do not match (null array vs array of length 8)

Question

I was wondering why I am some of my std_logic_vectors are showing up as null vectors especially when I specified the length already. I'd appreciate any help possible

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity counter8bits is
port(counter_enable, rst, clk : IN std_logic; counter_out : OUT std_logic_vector(7 to 0));
end entity counter8bits;

architecture counting_arc of counter8bits is
signal current_count : std_logic_vector(7 to 0);
type jstate is (nullState, start0, start1, change01, change10);
signal present_state : jstate;
signal next_state: jstate := nullState;



signal int_count: integer := 0;
begin

present_state <= next_state when clk'event and clk = '1';

current_count <= std_logic_vector(to_unsigned(int_count, 8)) when rising_edge(clk);
counter_out <= current_count;
stacking: process(present_state)
begin

next_state <= present_state;
int_count <= 0 when int_count = 255;    
                    case present_state is
                    
                        when nullState =>
                            if counter_enable = '0' then
                                next_state <= start0;
                            else
                                next_state <= start1;
                            end if;
                        
                        when start0 =>
                            if counter_enable = '1' then
                                next_state <= change01;
                                int_count <= int_count + 1;
                            else
                                next_state <= start0;
                            end if;
                        
                        when start1 =>
                            if counter_enable = '0' then
                                next_state <= change10;
                                int_count <= int_count + 1;
                            else
                                next_state <= start1;
                            end if;
                        
                        when change01 =>
                            if counter_enable = '0' then
                                next_state <= change10;
                                int_count <= int_count + 1;
                            else
                                next_state <= start1;
                            end if;
                        
                        when change10 =>
                            if counter_enable = '1' then
                                next_state <= change01;
                                int_count <= int_count + 1;
                            else
                                next_state <= start0;
                            end if;
                        when others =>
                            next_state <= nullState;                    

end case;

end process stacking;
end architecture counting_arc;

Here is the error: Fatal: (vsim-3420) Array lengths do not match. Left is 0 (7 to 0 (null array)). Right is 8 (7 downto 0).

Left refers to current_count and counter_out

This would be a simulation error that can't be duplicated without a [mcve], here providing a testbench. `signal current_count : std_logic_vector(7 to 0);` has a null range (IEEE Std 1076-2008 5.3.2.2 Index constraints and discrete ranges). Change the `7 to 0` to `7 downto 0`. Without wondering why or asking for nebulous help consider [ask], providing a minimal, complete, and verifiable example as well as a specific question. There isn't a duplicate question with a null range. — user16145658, Sep 13 '21 at 06:32
Please clarify your specific problem or provide additional details to highlight exactly what you need. As it's currently written, it's hard to tell exactly what you're asking. — Community, Sep 19 '21 at 05:06

score 1 · Accepted Answer · answered Sep 13 '21 at 06:25

A null range occurs when you specify the values in the wrong direction. Here you have specified both current_count and counter_out as 7 to 0. Using to is an ascending range, hence the first number should be the lower one. Similarly, downto is a descending range and should have the higher value on the left.

Here, I suggest you replace to with downto, as this is generally convention.

VHDL Modelsim: Array lengths do not match (null array vs array of length 8)

1 Answers1