VHDL - Why is it bad practice to not include an else-condition in a "process" block?

Question

I'm watching a beginner tutorial on VHDL. The lecturer says that it's bad practice to not include an else-condition inside a "process" block because it will create a latch and is bad for timing in advance circuits. He said that including an else-condition will create a mux instead and is better to use in most case. Why is that? snippet from lecture video

Why is a latch design bad for timing and what makes the mux design better?

On creating latches: IEEE Std 1076.6-2004 (RTL Synthesis, withdrawn) 6.2.1.1 Level-sensitive storage from process with sensitivity list "A level-sensitive storage element shall be modeled for a signal (or variable) when all the following apply: a) The signal (or variable) has an explicit assignment. b) The signal (or variable) does not have an execution path with as a condition. **c) There are executions of the process that do not execute an explicit assignment (via an assignment statement) to the signal (or variable)**." `out1 <= not en or a;` Dataflow, need a better example. — user16145658, Aug 12 '21 at 16:17
Your picture second snippet doesn't describe a multiplexer with one input stuck at a logic level. It will get optimized. — user16145658, Aug 12 '21 at 16:22
The [previous slide](https://www.youtube.com/watch?v=z4eqE7srNyU) (at 16:35). An accidentally inferred latch takes more device resources and as a result can complicate timing analysis. The message here isn't to model multiplexers but to avoid inadvertent latches. — user16145658, Aug 12 '21 at 23:25
It is not bad or good in absolute. It has an impact on the synthesis result. If you are designing a combinatorial process, by definition you do not want memory elements in the synthesized hardware. In this case you **must** guarantee that each output signal (any signal that can be assigned in the process) is **always** assigned at least once **every time** the process resumes. Else you somehow tell the synthesizer: "_and in all other cases this signal keeps its previous value_". And guess how we "_keep a previous value_" in digital hardware? With a latch. — Renaud Pacalet, Aug 13 '21 at 13:04
So, if you don't want latches to be inferred one possibility is to always have an `else` clause in `if` statements where signals are assigned. And a `default` choice in `case` statements where signals are assigned. But there are other ways. You can for instance unconditionnally assign a default static value to all signals at the beginning of the process. And beware the variables: signals are not the only cause of unwanted memory elements... — Renaud Pacalet, Aug 13 '21 at 13:09

score 2 · Accepted Answer · answered Aug 12 '21 at 17:41

The point is to make VHDL code that results in the design you want, and the risk is that you will inadvertently create a latch.

There are several basic constructions in VHDL, that can illustrate this.

Mux by process with if-then-else, can be made with this code:

process (all) is  -- Mux
begin
  if sel = '0' then
    z <= a;
  else
    z <= b;
  end if;
end process;

Mux by process with if-then and default assign, can be made with this derived code:

process (all) is  -- Mux
begin
  z <= b;  -- Default b, thus for sel = '1', since no overwrite
  if sel = '0' then
    z <= a;
  end if;
end process;

However, if you want to make a mux, then a better coding style is by continuous assign with this code:

z <= a when (sel = '0') else b;

Finally, what can lead to a latch with a process, is if the resulting output is not assigned in all branches of the code. That can occur, if the if-then does neither have an else, nor a default assign to the output, like this code:

process (all) is  -- Latch
begin
  if en = '1' then
    q <= d;
  end if;
end process;

So a good rule when designing combinatorial logic using a process, is to have an initial line that makes a default assignment to the resulting output, for example just assing undefined 'X'. A latch is thereby avoided, and functional verification should catch the undefined 'X', if this is a bug.

Also, remember to check the syntheis report for warnings about created latches, since that is most likely a bug in the design.

VHDL - Why is it bad practice to not include an else-condition in a "process" block?

1 Answers1