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i'm writing a verilog program. When i compile, there is no error. But when i simulate this program, there is an error: "MixColumns.v(14): (vopt-7063) Failed to find 'return' in hierarchical name 'return'." What should i do to fix this problem ? Thank you very much Here is my Verilog code

module MixColumns(
  input        [127:0] before_MixColumns,
  output  reg  [127:0] after_MixColumns
);

function  [7:0] mul_2;
  input [7:0] a;
  begin
  mul_2 = (a[7] == 1) ? ((a << 1) ^ 8'b00011011) : (a << 1);
  end
endfunction

function reg [7:0] mul_3 (input [7:0] a);
  return (a ^ mul_2(a));
endfunction

function reg [31:0] matrix_mul_word (input [31:0] a);
  begin
  matrix_mul_word[31:24] = mul_2(a[31:24]) ^ mul_3(a[23:16]) ^       a[15:8]  ^       a[7:0]  ;
  matrix_mul_word[23:16] =       a[31:24]  ^ mul_2(a[23:16]) ^ mul_3(a[15:8]) ^       a[7:0]  ;
  matrix_mul_word[15:8]  =       a[31:24]  ^       a[23:16]  ^ mul_2(a[15:8]) ^ mul_3(a[7:0]) ;
  matrix_mul_word[7:0]   = mul_3(a[31:24]) ^       a[23:16]  ^       a[15:8]  ^ mul_2(a[7:0]) ;
  end
endfunction

always @*
begin
  after_MixColumns[127:96] = matrix_mul_word(before_MixColumns[127:96]);
  after_MixColumns[95:64]  = matrix_mul_word(before_MixColumns[95:64] );
  after_MixColumns[63:32]  = matrix_mul_word(before_MixColumns[63:32] );
  after_MixColumns[31:0]   = matrix_mul_word(before_MixColumns[31:0]  );
end

endmodule

1 Answers1

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Your filename "MixColumns.v" is being interpreted as Verilog, but the return statement is a feature of SystemVerilog. Also, Verilog requires the use of begin/end bracketing around the procedural blocks of functions and tasks.

Change your filename to have a *.sv file extension.

dave_59
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