Not understanding vhdl online compiler error

Question

i am using an inline compiler (https://www.edaplayground.com/) and im not understanding the online compilers error message. I am trying to build the boolean expression (a * !b) + (b * !c) + (!b * c).

My code is:

library IEEE;
use IEEE.std_logic_1164.all;

ENTITY (MySimp) IS
PORT (A: in STD_LOGIC;
      B: in STD_LOGIC;
      C: in STD_LOGIC;
      Z: out STD_LOGIC;
 );
End MySimp;

ARCHITECTURE (details) OF (MySimp) IS
BEGIN 
PROCESS
VARIABLE D, E, F: STD_LOGIC;
BEGIN
IF A AND (NOT B)= '1' THEN D:= '1';
ELSE D:= '0';
END IF:

IF B AND (NOT C)= '1' THEN E:= '1';
ELSE E:= '0';
END IF:

IF C AND (NOT B)= '1' THEN F:= '1';
ELSE F:= '0';
END IF:

Z <= D OR E OR F;

END PROCESS;
END details;

ErrorMessage

from the error message and the .sv, I would bet you tried to compile the code as (system) verilog instead of VHDL! — B. Go, Dec 02 '19 at 20:03
I am not familiar with this compiler, thank you. Now im getting a different error message: Aldec, Inc. VHDL Compiler, build 2017.02.99 VLM Initialized with path: "/home/runner/library.cfg". DAGGEN WARNING DAGGEN_0523: "The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available." COMP96 File: design.vhd COMP96 File: testbench.vhd COMP96 ERROR COMP96_0018: "Identifier expected." "design.vhd" 4 8 COMP96 ERROR COMP96_0016: "Design unit declaration expected." "design.vhd" 4 9 — DEN, Dec 02 '19 at 20:09
COMP96 ERROR COMP96_0018: "Identifier expected." "design.vhd" 13 14 COMP96 ERROR COMP96_0016: "Design unit declaration expected." "design.vhd" 13 15 COMP96 ERROR COMP96_0016: "Design unit declaration expected." "testbench.vhd" 4 0 COMP96 Compile failure 5 Errors 0 Warnings Analysis time : 0.0 [ms] Exit code expected: 0, received: 1 — DEN, Dec 02 '19 at 20:10
I never saw the name of the objects, here the entity, being in (). Remove them, it's exactly at line 4 char 8 as the error says — B. Go, Dec 02 '19 at 20:12
From the image link for your error message you've told whatever tool that you've provided a SystemVerilog design when in fact you've provided a VHDL design incidentally [containing syntax and semantic errors](https://i.stack.imgur.com/a3kRt.jpg). — , Dec 02 '19 at 20:14
Note your process is also missing a process sensitivity list. Not an error but will prevent simulation finishing. The process will never suspend. Simulator vendors sometimes include a method of detecting the problem. — , Dec 02 '19 at 20:18
One of the great things about EDA Playground is that it allows you to share your code by posting its URL, eg https://www.edaplayground.com/x/9 .Were you to do that, we could see what you're seeing. — Matthew Taylor, Dec 02 '19 at 20:21

score 0 · Answer 1 · answered Dec 03 '19 at 14:07

As the error shows, you are compiling a VHDL file (.vhd) as a (System) Verilog file (.sv). Those are two different hardware description languages. In the Languages and Libraries tab on the left, you need to set the Testbench + Design to VHDL.

But there's a problem in your code. The process statement doesn't have a sensitivity list. HDLs are usually parallel languages, which means you need to indicate when a process needs to be triggered: else it will try to loop indefinitely in an infinitesimal time. You either need to add a wait-statement, to stop the loop, or implicitly do that by adding the trigger signals to the process sensitivity list. e.g.

process (a,b,c)

There are more semantical issues with your code. I added them in comments

library ieee;
use ieee.std_logic_1164.all;

entity MySimp is -- no braces around the name
    port (
        a: in  std_logic;
        b: in  std_logic;
        c: in  std_logic;
        z: out std_logic -- no semicolon
    );
end entity;

architecture arch of MySimp is
begin 
    process(a, b, c)
        variable d, e, f: std_logic;
    begin
        if (a and (not b))= '1' then -- add braces around the logic expression
            d:= '1';
        else
            d:= '0';
        end if; -- semicolon instead of colon

        -- alternative method 1
        if b='1' and c='0' then
            e:= '1';
        else
            e:= '0';
        end if;

        -- alternative method 2
        f := c and (not b);

        z <= d or e or f;
    end process;
    -- or replace the whole process by:
    --z <= (a and (not b)) or (b xor c);
    -- as (b and (not c)) or (c and (not b)) is an exclusive-or operation
end architecture;

Not understanding vhdl online compiler error

1 Answers1