Digital logic is the representation of signals and sequencing of a digital circuit. It is the basis for digital computing. (Note: There is the Electrical Engineering Stack Exchange website which is more suited to asking questions on hardware.)
Questions tagged [digital-logic]
229 questions
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16-bit floating point division (half-precision, excluding edge cases, just positive normal numbers)?
I tried to divide just a normal positive 16-bit-float-point number by a normal positive 16-bit-float-point number (half-precision, excluding edge cases). I did the sign with XOR gate, the exponent with 5-bit subtractor, but couldn't do the mantissa.…
Arthur
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Sequential Circuits for data select bits
How can I build a sequential circuit of data selects for seven segment display project using 4:1 Multiplexer?
I want to convert 2 single data input to 2 data select..
Saif Mohammed
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width mismatch in assignment; target has 10 bits, source has 8 bits error
I try to write VHDL code in Vivado to show multiply 8 bit number by 1,2,3,4.
i got the error in line (y <= ..) :
" width mismatch in assignment; target has 10 bits, source has 8 bits error in vhdl"
i dont understand whats the problem
library…
Eve
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How to write ALU control lines?
I know logical ADD in binary is 0010, and logical AND in binary is 0000. How do I go from this to a full operation?
aflo7
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2 answers
Multiplication table in VMLab / AVR
I am trying to figure out this question. I posted my code below. It doesn't work properly. it seems like its not multiplying the 2 least significant nibbles. I don't know AVR very well.
Write AVR that generates a multiplication table for SRAM…
Dawgburt
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VHDL - Upper digit output does not go up from '0000', when implementing two-digit-bcd-counter
I'm trying to implement two-digit-bcd-counter in VHDL, by referring to this diagram:
This is my code for it:
library ieee;
use ieee.std_logic_1164.all;
entity two_digit_bcd_counter is
port(
v_cc : in std_logic;
clk : in std_logic;
…
theCursedPirate
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2 answers
Output not as expected when implementing 4-bit SISO register in VHDL
I am trying to create a 4-bit SISO register in VHDL, and this is my main code:
library ieee;
use ieee.std_logic_1164.all;
entity right_shift_siso_reg_4 is
port(
D_in : in std_logic;
clk : in std_logic;
D_out : out std_logic
);
end…
theCursedPirate
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1 answer
How to represent multiple-output logic circuits in tree-based genetic programming
Consider the following digital logic circuit, which has multiple inputs and one output:
The logic circuit above can be represented in tree form:
This tree representation could then be used in a tree-based genetic programming framework to evolve…
Flux
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What does the double slash(transition 0 --> 1) mean in SRAM datasheet?
The following image is from the datasheet of SRAM IS64WV51216BLL(page 15).
It is a SRAM's write timing diagram.I don't know the meaning of double transitions for WE signal.I have circled it in red.
SRAM write timing diagram
Timing Diagram…
Jan
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How can w’xz + w’yz + x’yz’ + wxy’z be implemented with 4 NOR gates (+ inverters), given d = wyz
How can you implement the following function with only four NOR gates and inverters:
F = w’xz + w’yz + x’yz’ + wxy’z
d = wyz
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1 answer
Shifting in Verilog for multiplication
How does this line of code below works as the multiplication of (1024-31)?
The code is intended to be synthesized for FPGA, so shifting is used instead of direct division.
But what I do not understand is that how such shifting mimics the…
Blaco
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Verilog Binary Coded Decimal Adder Not Outputting Correctly
I'm new to Verilog and basically trying to teach myself a Digital Logic Design module for university. I am trying to write a BCD Adder in Verilog using two Full Adders with some logic in between for conversion to BCD when needed.
Here is my…
Wesley Shaw
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How to simplify sequential logic design by eliminating nested if-else statements
I have a design I've implemented using vhdl that is triggered based on a clock that sends an input signal to one of 8 output channels based on the sel input and also another 2 bit input. The elaborated design shows a lot of nesting due to the many…
Tellrell White
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If the PC register is simultaneously read and written, does its read data contain the previous data or the newly-written data?
If the PC register is simultaneously read and written, does its read data contain the previous data or the newly-written data? Based on my understanding of sequential circuits, the effect of the write command does not instantly take effect in the PC…
marshblocker
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Yosys synthesys - is this opimum?
I'm using yosys to synthesize simple circuits and show how the result varies with the cell library.
However, it looks like the result is not well optimized.
I'm using the library vsclib013.lib downloaded from:…
etnapoli
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