0

Would you take a 7-bit logic variable as an input and return an 8-bit logic output with the parity bit being the MSB (leftmost bit) of the output? In a system that uses even parity you want the total number of 1 bits in the output vector to be even, right? Can the the unary ^ operator can be used to calculate even parity?

Trying to figure out what that would look like?

I started something like this:

Code for parity

Sorry if this is more than one question.

CEStudent
  • 5
  • 3
  • Please show us what you tried. We will not do your homework for you. We can give hints and address specific challenges. – Greg Jun 05 '20 at 00:36
  • Ok, I did an edit to show you the parity part I have so far, but I wouldn't know how to add an even parity bit with that bit being the MSB? Just suggestions or hints will be good to know. – CEStudent Jun 05 '20 at 01:39
  • Hint: search for “Verilog concatenation”. FYI, it’s better to post the actual code then a screenshot – Greg Jun 05 '20 at 04:21
  • yes, `^` can be used to check parity. Also look at the reduction `^` operator. – Serge Jun 05 '20 at 10:37

1 Answers1

0

I would do this like this:

input logic [N-1:0] data_in;
output logic [N:0] data_out;

assign data_out = {^data_in, data_in};

The ^ reduction operator does an XOR operation on all the bits in the operand. (So, it will return '1 if data_in has an odd number of ones.)

pc3e
  • 1,299
  • 11
  • 18