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The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is ? and also construct the circuit design.

My Approach:

I understand that minimum J&K Gate required is 3 and I have calculated the MSB of J&K i.e (J2&K2) is both 1. I can't understand how to realize the (j1&k1) and LSB (j0&k0) because there I only get 0 & don't care. I don't understand how to implement it using K-Map.

Rex5
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John Lucas
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1 Answers1

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I got it, J2 & K2 Will be 1 and J1 & K1 will be Q2.Q0 and J0 & k0 will be Q2 where J1= F(Q2,Q1,Q0)= Q2.Q0 =K1 similarly J0 = F(Q2,Q1,Q0)= Q2= K0.

John Lucas
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