I did a make (make rocket and make project), I met an error at the make project, because I have not yet a target board. So, project file for viva do is not completely generated. I need to add files manually.
Where is top module of rocket processor (standard configuration)?
Within fpga-zynq, the majority of the source is in src/verilog/Top.DefaultFPGAConfig.v, however src/verilog/rocketchip_wrapper.v is the highest-level file.
The top-level chisel file to generate Top.DefaultFPGAConfig.v is in rocket-chip/src/main/scala/RocketChip.scala.
