How can generate the 32-bit RISCV form chisel soure. What are the required modifications?

Question

According to the RISCV toolchain, we are generating the verilog files for Rocketchip as 64-bit. but we need 32-bit RISCV rocket chip. For that what are requirements and modifications in scala and chisel files.

Is it possible to generate the 32-bit Rocket core to do so.

score 1 · Accepted Answer · answered Apr 20 '15 at 16:22

1

Rocket is a RV64 implementation. Unfortunately it does not have a simple switch to make it RV32. Making it RV32 will require some modification, hopefully small.

answered Apr 20 '15 at 16:22

user2548418

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Could you give some details on possible areas in the architecture that need to be modify. – Santhosh Kumar Apr 22 '15 at 05:46
In addition to the usual places (register widths and decode), the most awkward part will be the HTIF, which does not have a 32-bit version. – user2548418 Apr 22 '15 at 18:22

How can generate the 32-bit RISCV form chisel soure. What are the required modifications?

1 Answers1