clk event in chisel/scala

Question

Some time ago I wrote a vhdl code for a description of a D-type flip-flop. A piece of code was:

if (clk'event and clk='1') then
      q <= d;
end if;

How can I implement the following condition

clk'event

in scala/chisel language?

Answer 1

I'm a bit confused by your question - generally speaking, in Chisel there is no explicit clock. Also, there is no reason to write your own flip-flop as you would just use the Reg() construct provided by Chisel.

Now the exception is if you're dealing with multiple clock domains, in which case (according to the User Manual anyways),

val q = Reg(init=UInt(0), clock=myClock)

But unless you really know what you are doing with multiple clock domain HW design, I wouldn't suggest this.

Answer 2

I think the error is because you need to specify a default value for x and y by initializing the register: val x = Reg(init = UInt(0)) val y = Reg(init = UInt(0))

However, I think that this is what you actually want to be equivalent to the VHDL code:

  class DFF extends Module {
    val io = new Bundle
    {
      val d  = UInt(INPUT,  1)
      val q = UInt(OUTPUT, 1)
    }
    val out = Reg(UInt(width=1))
    when(Bool(true)) {
      out := io.d
    }
    io.q := out
  }

Answer 3

I thought of something like this:

class DFF extends Module { 

  val io = new Bundle { 
  val d  = UInt(INPUT,  1) 
  val ck  = UInt(INPUT, 1) 
  val q  = UInt(OUTPUT, 1) 
  val notq  = UInt(OUTPUT, 1)  
  } 

  val x  = Reg(UInt()) 
  val y  = Reg(UInt()) 

  x := io.q
  y := io.d

  when   (ck) { x := io.q; y:= x } 

}

What do you think?

Answer 4

Obviously it doesn't works. I modified the code in my DFF.scala:

import Chisel._  

class DFF extends Module 
{ 

val io = new Bundle 
{ 
  val d  = UInt(INPUT,  1)  
  val en = Bool(INPUT)
  val q  = UInt(OUTPUT, 1) 
  val notq  = UInt(OUTPUT, 1)  
} 

val x  = Reg(UInt()) 
val y  = Reg(UInt()) 

when (io.en) { x := io.d; io.q := y; y := x } 
io.notq := !(io.q)
}

But when i run this command:

sbt "run main --backend v"

I obtain this error:

[info] Set current project to dff-project (in build file:/home/francesco/Scrivania/Chisel-Project/CHILA/DFF-project/)
[info] Running TestMain main --backend v
backend elaborate
// COMPILING class DFF(0)
started inference
finished inference (2)
start width checking
finished width checking
started flattening
finished flattening (6)
[warn] NativeMethodAccessorImpl.java:-2: 'main' is an unknown argument. in class sun.reflect.NativeMethodAccessorImpl
[error]: NO DEFAULT SPECIFIED FOR WIRE: /*? in class DFF*/ Chisel.UInt(OUTPUT, width=1, connect to 0 inputs: ()) in component class DFF
Re-running Chisel in debug mode to obtain erroneous line numbers...
backend elaborate
// COMPILING class DFF(0)
started inference
finished inference (2)
start width checking
finished width checking
started flattening
finished flattening (6)
[warn] NativeMethodAccessorImpl.java:-2: 'main' is an unknown argument. in class     sun.reflect.NativeMethodAccessorImpl
[error] DFF.scala:6: NO DEFAULT SPECIFIED FOR WIRE: /*? in class DFF*/ Chisel.UInt(OUTPUT,    width=1, connect to 0 inputs: ()) in component class DFF in class DFF
[error] (run-main-0) java.lang.IllegalStateException: CODE HAS 1 ERRORS and 1 WARNINGS
java.lang.IllegalStateException: CODE HAS 1 ERRORS and 1 WARNINGS
at Chisel.ChiselError$.checkpoint(ChiselError.scala:119)
at Chisel.Backend.elaborate(Backend.scala:674)
at Chisel.VerilogBackend.elaborate(Verilog.scala:1128)
at Chisel.Driver$.execute(Driver.scala:67)
at Chisel.Driver$.apply(Driver.scala:39)
at Chisel.Driver$.apply(Driver.scala:44)
at Chisel.chiselMain$.apply(hcl.scala:113)
at TestMain$.main(main.scala:8)
at TestMain.main(main.scala)
at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:57)
at      sun.ref lect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:606)
[trace] Stack trace suppressed: run last compile:run for the full output.
java.lang.RuntimeException: Nonzero exit code: 1
at scala.sys.package$.error(package.scala:27)
[trace] Stack trace suppressed: run last compile:run for the full output.
[error] (compile:run) Nonzero exit code: 1
 [error] Total time: 1 s, completed 21-mag-2014 14.37.31

My main.scala is:

import Chisel._
import scala.collection.mutable.ArrayBuffer

object TestMain 
{
def main(args: Array[String]): Unit = 
{
    chiselMain(args, () => Module(new DFF()))   
}
}