I'd like to use Chisel to generate circuits from trees of if-then statements that I have in an XML format (PMML decision trees). Simple splits like
class Mod extends Module {
val io = new Bundle {
val x1 = UInt(INPUT, 8)
val x2 = UInt(INPUT, 8)
val choice = UInt(INPUT, 1)
val y = UInt(OUTPUT, 8)
}
when (io.choice === UInt(0)) {
io.y := io.x1
} otherwise {
io.y := io.x2
}
}
are human-readable and any complex expression can be evaluated with specific values in the testing suite. However, since I'll be generating nested splits programmatically from big XML files, it would help if I could inspect the tree of wires generated by Chisel, to be sure that it has the same structure.
I would have thought that I could inspect the graph through the Node's inputs and consumers fields. Using the example above, I would have thought that
val mod = new Mod
println(mod.io.x1.inputs, mod.io.x1.consumers)
println(mod.io.y.inputs, mod.io.y.consumers)
would have shown me intermediate nodes representing the when ... otherwise split and the := connections, which I could follow from x1 to y or from y to x1. However, all of these calls return empty ArrayBuffers. When I run similar circuits in the testing framework, it evaluates to the right thing, so presumably the testing framework is calling some function to build the graph that hasn't been called yet when I inspect it in the REPL (or I'm looking at the wrong fields). What do I need to do to see the graph data?
I could have asked if there are any tools for generating schematics from Chisel wiring or the Verilog output. However, I'd prefer to get my hands on the data itself so that I can do more with it (generate SVG files, or maybe convert it to GraphML and use a force-directed graph viewer...)
