Is it possible to use the Chisel HDL with a CPLD? If yes, have you tried it, could you share experience please?
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Is it possible to use the Chisel HDL with a CPLD? If yes, have you tried it, could you share experience please?
As Chisel generate Verilog code and the CPLD accept Verilog for synthesis, yes it's possible. I tested it with a CoolRunnerII from Xilinx. That works well.
