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I am referring to the following link, https://github.com/ucb-bar/zscale/issues/1 which denotes that zscale can be built from the rocket-chip generator with just different build option.

make CONFIG=ZscaleConfig MODEL=ZscaleTop verilog" instead.

However, from https://github.com/ucb-bar/rocket-chip.git repository, I find no such configuration 'ZscaleConfig' nor the ZscaleChip.scala in the proper directory. The only place I find those configuration and files are the following repository. gitlab.cs.fau.de/osek-v/osek-v/tree/a3c9431ee20f94bf2826251680de61b8d640b02d

Unfortunately, the repository seems to be somewhat out-of-date, and it won't build properly due to un-resolved tool dependencies (various proxies seems to be dead).

Is building the ZScale core from scala still a valid way of acquiring the verilog files, or downloading and using VScale the only way? If possible I'd like to build from scala, since it supports many more powerful functions, such as changing configuration in high-level language or C simulation (RTL simulation) that does not need VCS to run the tests.

Thank you all, in advance.

joist
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2 Answers2

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Z-scale is deprecated and no longer supported in the Rocket Chip Generator. After initializing the repo and building the RISC-V toolchain by following the steps in the Rocket Chip README, you can build a tiny core with:

cd vsim
make verilog CONFIG=TinyConfig

This builds a Rocket implementation that is similar in size and functionality to the old Z-scale core.

Ben
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  • That was what I thought so since there hasnt been any updates regarding zscale in a meanwhile. Thank you so much for confirming it. Ill try to check out how much the small config core can match zscale in terms of PPA or complexity. – joist Aug 06 '16 at 02:04
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Zscale was removed in https://github.com/ucb-bar/rocket-chip/commit/f52fc655a54bbfd3d5e89895cdd8152f5a77b69c#diff-0ff996c4528f4b67c36098dab7873f08 at 16 May 2016.

You may try older revision of rocket-chip.

osgx
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