"data to be connected 'chisel3.core.UInt@103' must be hardware, not a bare Chisel type" when rewrite OpenSoCFabric1.1.2 from Chisel2 to Chisel3

Question

I am trying to rewrite OpenSoCFaric-1.1.2 from chisel2 to chisel3. But I encounter error messages "data to be connected 'chisel3.core.UInt@103' must be hardware, not a bare Chisel type" for below code:

File: packettoFlit.scala class: PacketToFlit val flitWidth = Flit.fromBits(0.U, parms).getWidth

File:channel.scala object: Flit

object Flit {
    def head(h: HeadFlit) : Flit = {
        val f = new Flit(h.parms)
        f.x := f.union.pack("Head", h)
        f
    }

    def body(b: BodyFlit) : Flit = {
        val f = new Flit(b.parms)
        f.x := f.union.pack("Body", b)
        f
    }

    def fromBits(n: UInt, parms: Parameters) : Flit = {
        val f = new Flit(parms)
        f.x := n
        f
    }

    /*
    def zeroHead(parms: Parameters) : HeadFlit = {
        val x = new HeadFlit(parms)
        x.
    }
    */
}

And now I don't have good ideas about how to rewrite such code segments to fix the error. Could you give some help or suggestions ? Thanks a lot!

score 0 · Answer 1 · answered May 07 '18 at 16:47

0

We would need to see more of the error message (line number) and more of the code to provide a definitive answer, but our guess is that somewhere a UInt(x.W) is being used where a literal (y.U) is expected, or a Wire()/WireInit() wrapper is missing.

NOTE: LBL is actively migrating this code to Chisel3. You might be better off waiting for their work to be published.

answered May 07 '18 at 16:47

Jim Lawson

101
2

[error] (run-main-2) chisel3.core.Binding$ExpectedHardwareException: data to be connected 'chisel3.core.UInt@103' must be hardware, not a bare Chisel type chisel3.core.Binding$ExpectedHardwareException: data to be connected 'chisel3.core.UInt@103' must be hardware, not a bare Chisel type at chisel3.core.requireIsHardware$.apply(Binding.scala:31) at chisel3.core.Data.connect(Data.scala:291) at chisel3.core.Data.$colon$eq(Data.scala:363) at OpenSoC.Flit$.fromBits(channel.scala:100) at OpenSoC.PacketToFlit.(packetToFlit.scala:98) – Bibo May 08 '18 at 03:32
(line 98) PacketToFlit val flitWidth = Flit.fromBits(0.U, parms).getWidth – Bibo May 08 '18 at 03:34
def fromBits(n: UInt, parms: Parameters) : Flit = { val f = new Flit(parms) f.x := n (line 100, file channel.scala) f } – Bibo May 08 '18 at 03:35
Jim, thanks your response firstly. I figure out the key source code in commnets. – Bibo May 08 '18 at 03:36
Can you post the source code for `class Flit`? It looks to me like the issue is inside the construction of the Flit in `val f = new Flit(parms)` – Jack Koenig May 08 '18 at 20:24
Thank you for sharing the rest of the code. As indicated in the original answer, you need to wrap Chisel types in `Wire` when you expect them to be part of the hardware graph. Because class `Flit` extends `Bundle`, it is a Chisel data type, and if you want an instance of it to be part of the circuit you should wrap it in Wire, ie. `val f = new Flit(b.parms)` should be `val f = Wire(new Flit(b.parms))` – Jack Koenig May 09 '18 at 19:09

score 0 · Answer 2 · edited May 09 '18 at 05:05

Below is source code for class Flit.

class Flit(parms: Parameters) extends Bundle {
    val union   = new BitUnion(Map("Head" -> new HeadFlit(parms), "Body" -> new BodyFlit(parms)))
    val x       = UInt(union.width.W)
    val numVCs  = parms.get[Int]("numVCs")

    def asHead(dummy: Int = 0) : HeadFlit = union.unpack[HeadFlit]("Head", x)
    def asBody(dummy: Int = 0) : BodyFlit = union.unpack[BodyFlit]("Body", x)

    def whenHead(block: HeadFlit => Unit) { union.whenTag[HeadFlit]("Head", x)(block) }
    def whenBody(block: BodyFlit => Unit) { union.whenTag[BodyFlit]("Body", x)(block) }

    def isHead(dummy: Int = 0) : Bool = union.tagEquals("Head", x)
    def isBody(dummy: Int = 0) : Bool = union.tagEquals("Body", x)
    def isTail(dummy: Int = 0) : Bool = {
        val tailBit = Bool()
        when (isHead()) {
            tailBit := union.unpack[HeadFlit]("Head", x).isTail
        } .otherwise {
            tailBit := union.unpack[BodyFlit]("Body", x).isTail
        }
        tailBit
    }
    def getVCPort(dummy: Int = 0) : UInt = {
        val vcBits = UInt(log2Ceil(numVCs).W)
        when (isHead()) {
            vcBits := union.unpack[HeadFlit]("Head", x).vcPort
        } .otherwise {
            vcBits := union.unpack[BodyFlit]("Body", x).vcPort
        }
        vcBits
    }

    //override def clone = { new Flit(parms).asInstanceOf[this.type] }
    override def cloneType: this.type = new Flit(parms).asInstanceOf[this.type]
    // override def width : Int = {x.width}
}

Thanks a lot! Bibo

"data to be connected 'chisel3.core.UInt@103' must be hardware, not a bare Chisel type" when rewrite OpenSoCFabric1.1.2 from Chisel2 to Chisel3

2 Answers2