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I have a Peripheral which has a general layout as follows. The Block I have mentioned is not designed by me so, I want to inherit the module and make few internal signals as IO ports of the peripheral.

The Wire which needs to be converted as the ports is in a module instantiated using LazyModuleImp and replaces the comment Some Wire needs to be converted as a port pin in the following block.

package SomeBlock.SomePackage

import Chisel._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.Field
import freechips.rocketchip.subsystem.BaseSubsystem


case class SomeParams(
    //Some Parameters
}

class SomeBundle extends Bundle {
    // Some Port Pins
}

class SomeModule(params: SomeParams) extends LazyModule {
 // Some Logic
  lazy val module = new LazyModuleImp(this) {
    val io = IO(new SomeBundle {
      val clock  = Clock(OUTPUT)
      val reset = Bool(INPUT)
    })
    // Some logic
    // Some Wire needs to be converted as a port pin
  }
}

case object PeripherySomeModuleKey extends Field[SomeModuleParams]

trait HasPeripherySomeModule { this: BaseSubsystem =>
  val someParams= p(PeripherySomeModuleKey)
  val some = LazyModule(new SomeModule(someParams))
  // Logic to connect to TileLink Node
}

trait HasPeripherySomeBundle {
  val some: SomeBundle
}

trait HasPeripherySomeModuleImp extends LazyModuleImp with HasPeripherySomeBundle {
  val outer: HasPeripherySomeModule
  val some = IO(new SomeBundle)
  some <> outer.some.module.io
}

What are the ways I can add some more port pins to the design without modifying the actual design?

hitoswal
  • 11
  • 2
  • Some clarifying questions for you: what do you want to happen to those `Some Wire`? Do you want them to be accessible via memory-mapped registers? Brought out to top-level I/O pads? The answer will be somewhat different. Also, is this module written in Chisel, or are you needing to black box a verilog module? – user839768 Mar 01 '20 at 20:25
  • I want to bring that ```Some Wire``` to top-level I/O pads. And the module is defined using Chisel in the class ```SomeModule``` using ```LazyModuleImp```. – hitoswal Mar 02 '20 at 20:00

0 Answers0