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In the context of combinatorial logic synthesis (not simulation): When should a function be declared as automatic ? When should a function be declared as static ?

shaiko
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A function should never be declared with a static lifetime. There is no case where a function would be automatic by default and need to be explicitly declared static. (and this would be illegal do in a class method anyways).

There are cases where a function must be declared with automatic lifetime so it cn be called recursively and the arguments won't be overwritten.

This is the part of the subject of my DVCon2021 paper "The Life of a SystemVerilog Variable".

dave_59
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  • "A function should never be declared with a static lifetime." This confuses me a bit. Didn't you suggest (in the link below) to declare the function inside a class as static ? https://electronics.stackexchange.com/questions/549114/systemverilog-interface-definition-lint-error-message – shaiko Feb 20 '21 at 02:22
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    A static class method qualifier is not the same as a function with a static lifetime. The static keyword is overloaded. – dave_59 Feb 20 '21 at 02:37
  • I see. thanks for the explanation. I'll re-phrase my main question then: in the context of combinatorial logic synthesis (not simulation) - when should a function be declared with a static method qualifier ? and when with an automatic ? – shaiko Feb 20 '21 at 11:55
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    https://verificationacademy.com/forums/systemverilog/what-exact-difference-between-static-tasks/functions-and-automatic-tasks/functions-please-explain-clear-example#reply-44935 – dave_59 Feb 21 '21 at 07:26