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I want to design a gate-level combinational circuit that implements the below logic. Is it possible to do it without using Adder?

...
input  wire [3:0] in,
input  wire       sel,
output wire [3:0] out
...

assign out = ({4{sel}} & (~in + 1)) | ({4{~sel}} & in);

The above verilog code will be realized into - 4 inverters, 1 full adder and 1 multiplexer. Is it possible to optimize it further?

The idea is to incorporate sel in 2's complement logic and produce a gate circuit that consumes lesser number of gates than adder circuit. Is it really possible?

ashishdevre
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  • What language is your description in? Please edit your question to include the correct tags (e.g. `verilog` or `vhdl` or similar). And if you want to do it without a MUX then you should probably remove that tag? – Some programmer dude Nov 12 '17 at 04:22
  • Thanks for pointing it out. I have edited the question. – ashishdevre Nov 13 '17 at 04:37
  • You could use a 16-entry LUT to do the 2's compliment conversion. I'd be curious though to see the gate difference between that and the 4b adder. – ajcrm125 Nov 14 '17 at 13:53

1 Answers1

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Try using the Karnaugh map and solve for just the (~in + 1) term. If you set up the K-map and solve for one bit of the result at a time

// Input                               Result
// A B C D     -->  ~{A B C D}  --> ~{A B C D}+1  
// 0 0 0 0            1 1 1 1         0 0 0 0
// 0 0 0 1            1 1 1 0         1 1 1 1
// 0 0 1 0            1 1 0 1         1 1 1 0
// 0 0 1 1            1 1 0 0         1 1 0 1
// 0 1 0 0            1 0 1 1         1 1 0 0
// 0 1 0 1            1 0 1 0         1 0 1 1

... I'll let you write the rest of the map... but a few things start to pop out.

The Result bit D, is always the same as the Input D The Result bit C appears to be a Input C XOR Input D

If you do some more K map, you will probably find a logical expression for Result bits A and B

Rich Maes
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