Key expansion module of AES on Xilinx : error : multisouce on signal

Question

This is code written in VHDL on Xilinx 9.2 ise. NK = 4 NR = 10; VALUE=43; K_IN is the key from the user in the form of

type STATEX is array(0 to 3, 0 to 3) of std_logic_vector (7 downto 0);

K_OUT is the output of

type KEYWORD is array (0 to 43) of std_logic_vector (31 downto 0);

subword is a component which returns the Sbox value of 32 bit input.

I cannot figure out where in K_IN and K_OUT multi source of signal is happening. Please help me figure out and solve this problem. Thank you.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.STATEVARIABLE.ALL;

ENTITY KEY_MODULE IS
    PORT (  
        SYS_CLK:    IN  STD_LOGIC;
        RST:        IN  STD_LOGIC;
        S:          IN  STD_LOGIC;
        K_IN:       IN  STATEX; ---- FOR 128 BITS KEY
        K_OUT:      OUT KEYWORD
    );

END KEY_MODULE;

ARCHITECTURE BEHAVIORAL OF KEY_MODULE IS
    SIGNAL SWORD_OUT:   STD_LOGIC_VECTOR(31 DOWNTO 0);
    SIGNAL TEMP:        STD_LOGIC_VECTOR(31 DOWNTO 0);
    SIGNAL TEMP_WORD:   KEYWORD;

    COMPONENT SUBWORD
        PORT (
            SYS_CLK:    IN  STD_LOGIC;
            RST:        IN  STD_LOGIC;
            S:          IN  STD_LOGIC;
            WORD:       IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
            SWORD:      OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
        );
    END COMPONENT;

    FUNCTION ROTWORD (A: STD_LOGIC_VECTOR(31 DOWNTO 0)) 
            RETURN STD_LOGIC_VECTOR IS
        VARIABLE OUTPUT: STD_LOGIC_VECTOR(31 DOWNTO 0);
    BEGIN
        OUTPUT := A(23 DOWNTO 16) & A(15 DOWNTO 8) & A(7 DOWNTO 0)& 
                  A(31 DOWNTO 24); 
        RETURN OUTPUT;
    END FUNCTION;

    FUNCTION RCON (I: INTEGER) RETURN STD_LOGIC_VECTOR IS
        VARIABLE OUTPUT: STD_LOGIC_VECTOR(31 DOWNTO 0);
        VARIABLE TEMP1: STD_LOGIC_VECTOR(7 DOWNTO 0);
        VARIABLE NUM: INTEGER;
    BEGIN
        NUM :=  2**(I-1)  REM 229 ;
        TEMP1 := CONV_STD_LOGIC_VECTOR(NUM,8);
        OUTPUT := TEMP1 & X"000000" ;
        RETURN OUTPUT;
    END FUNCTION;

BEGIN

G1: FOR J IN 0 TO NK-1 GENERATE
        TEMP_WORD(J) <= K_IN(0,J) & K_IN(1,J) & K_IN(2,J) & K_IN(3,J);
    END GENERATE G1;

G2: FOR J IN NK TO VALUE GENERATE
        TEMP <= TEMP_WORD(J-1);
G3:     IF J MOD NK = 0 GENERATE
UUT1 :      SUBWORD 
                PORT MAP (
                    SYS_CLK => SYS_CLK,
                    RST => RST,
                    S => S,
                    WORD => ROTWORD(TEMP),
                    SWORD => SWORD_OUT
                );
            TEMP <= SWORD_OUT XOR RCON(J/NK);
        END GENERATE G3;

G4:     IF (NK > 6 AND (J MOD NK) = 4)  GENERATE
UUT2 :      SUBWORD 
                PORT MAP (
                    SYS_CLK => SYS_CLK,
                    RST => RST,
                    S => S,
                    WORD => TEMP,
                    SWORD => SWORD_OUT
                );
            TEMP <= SWORD_OUT;
        END GENERATE G4;
        TEMP_WORD(J) <= TEMP_WORD(J-NK) XOR TEMP;
    END GENERATE G2;

    K_OUT <= TEMP_WORD;

END BEHAVIORAL;

output error:

ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_OUT<10><31>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_OUT<10><30>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_OUT<10><29>>
ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_OUT<10><28>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_OUT<10><27>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_OUT<10><26>>
ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_OUT<10><25>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_OUT<10><24>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><1><7>>
ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><1><6>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><1><5>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><1><4>>
ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><1><3>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><1><2>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><1><1>>
ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><1><0>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><2><7>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><2><6>>
ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><2><5>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><2><4>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><2><3>>
ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><2><2>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><2><1>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><2><0>>
ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><3><7>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><3><6>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><3><5>>
ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><3><4>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><3><3>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><3><2>>
ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><3><1>> ERROR:Xst:528 - Multi-source in Unit <KEY_MODULE> on signal <K_IN<3><3><0>>

Your code is not a [Minimal, Complete and Verifiable example](https://stackoverflow.com/help/mcve) lacking declarations for entity SUBWORD , types STATEX and KEYWORD or the apparent constant with a base type of integer VALUE. Further there are no drivers for KEY_IN locally, meaning the errors associated with it are external to the code you have shown (It's illegal to drive a port of mode IN). Ril_Dark addresses multiple drivers for TEMP_WORD. — , Sep 15 '17 at 23:57
@user1155120 although you have a point, I don't think this two and a half year old question is still open... — JHBonarius, Sep 16 '17 at 07:40

Ril Dank · Answer 1 · 2015-02-08T19:23:20.727

0

I would try to encapsulate all the assignations to TEMP_WORD (which is K_OUT) under one process or generate block (ex: G1 and G2 under Gmain). Even though the indices don't seem to overlap, the compiler might still not accept that.

EDIT :

Reading your code more closely, your problem comes from the multiple assignations of the TEMP signal which is then assigned to TEMP_WORD -> K_OUT

Moreever, you have TEMP <= TEMP_WORD(J-1); and TEMP_WORD(J) <= TEMP_WORD(J-NK) XOR TEMP; in the beginning and end of G2: which creates a combinatorial loop.

edited Feb 08 '15 at 19:23

answered Feb 06 '15 at 10:12

Ril Dank

105
1
11

under process we cannot call a component. for that we have to use generate stmnt. and putting it uder Gmain it gives me error for k_out 31 to 0. – Nilima Parmar Feb 06 '15 at 10:58

Key expansion module of AES on Xilinx : error : multisouce on signal

1 Answers1