VHDL Coding: 10 bit Decimal conversion to BCD is it possible?

Question

Good Day,

My latest assignment is to convert the 10 bit decimal (since the maximum decimal number of 10 bit is 1023) to 16 bit BCD. When the input decimal is greater than or equal to 1024, then the error waveform will go high. The whole module of course is connected to a clock. I don't know how can I implement this in VHDL coding but I have some few suggested ideas on how can I make it work:

First, I could implement the use of TWO MODULES where the output of the first block will be connected to the second block with the same clock. The output of the first block is the binary of the input where the error is equal to 1 when the decimal input is greater than 1023.

The second one is to just use the one module technique where the input decimal is directly converted to 16-bit BCD where the error is one if the input decimal is greater than 1023.

Can anyone help me on how to code the decimal to bcd conversion using VHDL. A little help is much appreciated. Thank you

Well, my fellow classmate figure out how it will gonna do. He use the MODULO function with the division. I'll go upload the code here but since our introduction to VHDL in class only use the simulation, then we don't know if it is "synthesizable". — c2s1, Aug 23 '17 at 02:52
A simple search would have shown you dozens of existing questions asking about BCD converters. — scary_jeff, Aug 23 '17 at 08:52
General homework question, no specific VHDL language issue, no research done — EML, Aug 23 '17 at 13:29
I'm sorry, but this is not possible. Why bother to try to solve this problem at all? — andrsmllr, Aug 24 '17 at 07:58

score -1 · Answer 1 · answered Aug 23 '17 at 02:57

Well, my classmate figure out the problem on how to code this using the MOD function. Here's the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity dec_to_bcd is
    Port ( Ina : in  STD_LOGIC_VECTOR (9 downto 0);
           clk : in  STD_LOGIC;
           Outa : out  STD_LOGIC_VECTOR (15 downto 0);
           err : out  STD_LOGIC);
end dec_to_bcd;

architecture Behavioral of dec_to_bcd is

begin
process (clk)
begin
    if clk='1' and clk'event then
        if (conv_integer(Ina) >= 1024) then
            err <= '1';
        else
            Outa(15 downto 12) <= conv_std_logic_vector((conv_integer(Ina) / 1000),4);
            Outa(11 downto 8) <= conv_std_logic_vector((conv_integer(Ina) / 100)MOD 10,4);
            Outa(7 downto 4) <= conv_std_logic_vector((conv_integer(Ina) / 10)MOD 10,4);
            Outa(3 downto 0) <= conv_std_logic_vector((conv_integer(Ina))MOD 10,4);
        end if;

end if;
end process;
end Behavioral;

Since our introduction to VHDL in class only use the simulation, then we don't know if it is "synthesizable". Any suggestion on how to improve this code is warmly welcome. Thanks :)

Do not `use IEEE.STD_LOGIC_ARITH.ALL;` or `use IEEE.STD_LOGIC_UNSIGNED.ALL`. You should `use ieee.numeric_std.all;`, which gives you arithmetic using types signed and unsigned, along with casts and conversion functions for `std_logic_vector` and `integer`. — scary_jeff, Aug 23 '17 at 08:50
Okay, thank you for the tip. Your help is much appreciated :) — c2s1, Aug 24 '17 at 01:25

vipin · Answer 2 · 2017-10-31T15:46:44.280

You can use the Double dabble algorithm for this purpose. I have written a vhdl function for this in my blog, which basically converts 8 bit binary to 12 bit BCD. You can use the same concept for 10 bit binary numbers too.

function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable bcd : std_logic_vector(11 downto 0) := (others => '0');
variable bint : std_logic_vector(7 downto 0) := bin;

begin
for i in 0 to 7 loop  -- repeating 8 times.
  bcd(11 downto 1) := bcd(10 downto 0);  --shifting the bits.
  bcd(0) := bint(7);
  bint(7 downto 1) := bint(6 downto 0);
  bint(0) :='0';


  if(i < 7 and bcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
    bcd(3 downto 0) := bcd(3 downto 0) + "0011";
  end if;

  if(i < 7 and bcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
    bcd(7 downto 4) := bcd(7 downto 4) + "0011";
  end if;

  if(i < 7 and bcd(11 downto 8) > "0100") then  --add 3 if BCD digit is greater than 4.
    bcd(11 downto 8) := bcd(11 downto 8) + "0011";
  end if;

end loop;
return bcd;
end to_bcd;

The code is synthesisable too.

Although it is synthesizable, you are using 3 comparators and 3 additions in series, which will have quite an impact on timing performance. Also, it seems you are using `std_logic_arith`<- don't. Use `unsigned` types. And please fix your indentation. — JHBonarius, Oct 31 '17 at 15:43

VHDL Coding: 10 bit Decimal conversion to BCD is it possible?

2 Answers2