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How do I assign a input-bus to an output-bus without having to assign every index (without loops).

I had something like that in mind:

module test(input [2:0] in, input CLK, output [2:0] out);
reg [2:0] state;
always @(posedge CLK) state <= in; 
assign out = state;

But this code doesn't work. I need : out[0] = in[0], out[1] = in[1], out[2] = in[2].

k t
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1 Answers1

2

Issues with the giving code:

  • CLK is defined as a 3-bit input, should be 1-bit
  • Missing semicolon (;) on the first line
  • Missing keyword endmodule

FYI: By declaring out as an output reg the intermediate state can be omitted.

module test (
    input      [2:0] in,
    input            CLK, // <-- CLK is single bit
    output reg [2:0] out // <-- out is a reg type
    ); // <-- semicolon here

  always @(posedge CLK)
    out <= in; // <-- synchronous assignment

endmodule // <-- keyword
Greg
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  • My output is a wire and predefined. I cannot change it in the header.(sorry for the mistakes and thanks for correction!!) – k t Dec 16 '14 at 17:40
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    I'm a little confused with your comment. Either your header is blatantly wrong by having CLK defined a 3-bit input. Or there is a Xilinx limitation/criteria I not familiar with. Or there is a misconception about signal scoping. `out` can be declared as an `output reg` only in the module driving it, all other parts of the design should treat is as a `wire`. It is _okay_ to have the output be a `wire`. I don't recommend it because it adds extra steps and more lines of code. – Greg Dec 16 '14 at 18:21
  • My header looks like this `(input [2:0] in, input CLK, output wire [2:0])` . CLK is not 3-bit wide. What extra steps are needed? – k t Dec 16 '14 at 18:41
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    I'm assuming there is a typo and the header is: `(input [2:0] in, input CLK, output wire [2:0] out)`. The extra step is to declare an intermediate `reg` then assign out to it, just as you did with `state`. FYI: `assign out = state;` is full bit assignment and is synonymous with `assign out[2:0] = state[2:0];`. – Greg Dec 16 '14 at 18:57
  • Ok, thanks! Now, I see - I didn't setup my testbench correctly. Sorry, about the syntax mistakes. So far, verilog is very confusing to me. – k t Dec 16 '14 at 20:36