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I am trying to synthesize a code, there is no error but in map report I got this informational message as follows:-

INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.

Arslan
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  • Do you have "speed critical single ended outputs" in your design? – Jonathan Drolet Apr 21 '15 at 13:30
  • I am sorry but first I need to know that what is speed critical single ended output? – Arslan Apr 21 '15 at 13:32
  • Do you have any output interface with an external chip that runs at high speed. High is relative, but let's say beyond 100MHz? – Jonathan Drolet Apr 21 '15 at 13:34
  • No, I will try to connect my output to LED's or LCD at the most..... – Arslan Apr 21 '15 at 13:42
  • Then ignore that message – Jonathan Drolet Apr 21 '15 at 13:42
  • Yes Sir, I can ignore it, but it would have been better if could improve its delay a little bit more, even if it will remain on paper only and plus it will add to our knowledge if we find some way to do it.......By the way Thank you very much for your concern....... – Arslan Apr 21 '15 at 13:58
  • As Russel pointed out, there are plenty of guides and example of .UCF files that set the slew rate. I feel you really shouldn't concern yourself with that unless your design is working, or is not working because of that. "Improve delay a little bit more", we are talking nanoseconds here, beside, it increase power consumption and slew should only be changed when necessary. – Jonathan Drolet Apr 21 '15 at 14:03
  • You haven't made it clear where you are constraining the slew rate. Is this done in UCF, etc. or as an attribute? (and hence the VHDL tag). –  Apr 21 '15 at 17:01
  • I'm not quite sure but a fast slew rate should result in a higher power consumption. – Paebbels Apr 21 '15 at 19:23

2 Answers2

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That message is just a "For your information" message because you are letting the tool automatically assign the default slewrate on all pins. It can be ignored. However, you will probably get rid of the warning if you explicitly specify the slewrate of your IOs instead of letting the tool assign the default slewrate. You can probably explicitly specify a SLOW slewrate for each pin, and get rid of the warning that way.

Here is the userguide for constraining IOs (slew is on page 251): http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/cgd.pdf As a FPGA developer you should absolutetly learn how to constrain IOs. It is a quite important. For each pin you should always specify properties such as: pin number, slew, IO-standard, pull-up/down/none resistor, current, and load.

Regarding selecting fast or slow slewrate. You shall always select the slowest possible slewrate which is fast enough for your design. While faster slewrate reduces delay by a nanosecond or so, that is the only advantage it has. But it has many disadvantages, particularly degraded signal quality in the form of ringing, electromagnetic emissions, and extremely high current surges when multiple pins change state at the same time. This can result in very difficult to debug stability problems, which you do not want.

Timmy Brolin
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Try googling that info message, this is the first page that popped up:

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/designating-outputs-as-fast-outputs/td-p/247578

You can add slew rate constrains in your constraint file, read the Constraints Guide that Austin linked to on that Xilinx forum to see how to do this. As a note, you should only need to increase the slew rate of signals that toggle "quickly"

Russell
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  • I had already tried that before coming here. But the problem is that even after going through that user constraint guide, I was not able to make things right..... – Arslan Apr 21 '15 at 13:23
  • If you are having specific problems with applying IO constraints, then you should create a new stack overflow question about that. The answer to the question you have asked here is simply that you are missing explicit IO constraints. – Timmy Brolin Apr 21 '15 at 20:55