Is there a way to show variables in ISim?

Question

I'm trying to moniter the state of this variable:

shared variable Div16 : integer := 0;

But I am recieving this error in ISim:

ISim does not yet support tracing of VHDL variables.

Can you convert the variable to a signal within the testbench file? Or is there any other way to show this value changing as a waveform?

Complete Code:

entity MAIN_UART is
  generic (
    DIVISOR: natural := 120 -- DIVISOR = 50,000,000 / (16 x BAUD_RATE)
    -- 9600 -> 120
     -- 19200 -> 60
  );
  port (
    CLK: in std_logic;        -- clock
    RST: in std_logic         -- reset
  );
end MAIN_UART;

architecture Behavioral of MAIN_UART is

    signal Top16: std_logic; -- 1 clk spike at 16x baud rate    
    shared variable Div16 : integer := 0;

--  constant COUNTER_BITS : natural := integer(ceil(log2(real(DIVISOR))));

begin

-- --------------------------
-- Clk16 Clock Generation
-- --------------------------
    process (RST, CLK)
    begin
        if RST='1' then
            Top16 <= '0';  --good
            Div16 := 0;
        elsif rising_edge(CLK) then
            Top16 <= '0';
                if Div16 = Divisor then
                    Div16 := 0;
                    Top16 <= '1';  --good
                else
                    Div16 := Div16 + 1;
                end if;
        end if;
    end process;

end Behavioral;

You should declare the variable in the process, so it's not needed to declare it as shared. — Paebbels, Aug 19 '15 at 18:48

score 3 · Accepted Answer · answered Aug 19 '15 at 15:19

3

You can add:

signal Div16_signal : integer := 0;

And then at then end of your process add:

Div16_signal <= Div16;

answered Aug 19 '15 at 15:19

0xMB

871
1
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15

1

If you want iSim to offer other radices than the default, you need to declare the div16 signal as for example SIGNED and add a conversion to the variable to signal assignment :). – Paebbels Aug 19 '15 at 15:35
@Paebbels So would the signal declaration look like this "signal Div16_signal : unsignedinteger := 0;" and I'm not entirely sure what the variable to conversion statement would look like – VKkaps Aug 19 '15 at 16:01

score 0 · Answer 2 · answered Aug 19 '15 at 17:06

In addition to the answer of @0xMB.

If you want iSim to offer other radices than the default, you need to declare the div16 signal as for example SIGNED and add a conversion to the variable to signal assignment.

architecture rtl of myEntity is
  signal DBG_div16  : SIGNED(31 downto 0);
begin

  process(clk)
    variable div16 : integer := 0;
  begin
    -- some code

    -- assign the variable to a signal, so iSim can display it's value
    DBG_div16 <= signed(div16, DBG_div16'length);
  end process;

end architecture;

Is there a way to show variables in ISim?

2 Answers2