Why in the design we do not use or consider "D0" & "D20" drive strength cell in design?
is there are any reason related to the chip aging? if yes please explain me
or if you know other factors except than "chip aging" then please explain
Why in the design we do not use or consider "D0" & "D20" drive strength cell in design?
is there are any reason related to the chip aging? if yes please explain me
or if you know other factors except than "chip aging" then please explain
Since this is tagged as vlsi, the context of your question pertains to chip design. D0's are "typically" not used in because of higher process variation in lower sized drivers. The intuition is as follows W/L is small for D0 => \delta W/W (process variation) is higher. In other words, the delay variation becomes too high to be acceptable. That said, I have seen D0s offered for older technology nodes.
For, higher strength D20, they don't suffer from process variation issues, but, power considerations may not allow their usage. Additionally bigger cells would have bigger parasitic capacitances (again a power/performance consideration)