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I am new to VHDL programming. The project regards detecting faults in a memory array. I have obtained the faulty data and address. Now I want to get the corresponding row or column number of the particular address found in memory array. Code for achieving this in VHDL would be appreciated! Here is my simple code for creating SRAM and performing read and write operation:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity memory is   

port(   Clock :     in std_logic;     
      Write :       in std_logic;
      Read  :  in std_logic;
      -- Addr  :     in std_logic_vector(7 downto 0);
     Data_in :  in std_logic_vector(7 downto 0);
     Data_out:  out std_logic_vector(7 downto 0);
    Data_out_f: out std_logic_vector(7 downto 0);
     add_out  : out std_logic_vector(7 downto 0)

);
end memory;

architecture behav of memory is

--Declaration of type and signal of a 256 element RAM
--with each element being 8 bit wide.
type ram_type is array (0 to 255) of    std_logic_vector(7 downto 0);
signal tmp_ram: ram_type:=(others=>"00000000");

signal Addr  :  std_logic_vector(7 downto 0):="00000000";

begin   

process(Clock,addr,Write,read)
begin

if (Clock'event and Clock='1') then

 if addr <"00001111" and write='1' and Data_in(7)/='U' then    

    addr <= addr + '1';

 elsif  addr >"00000000" and read='1' then

    addr <= addr - '1';    

 end if;

end if;  

end process;               

-- Write Functional Section
process(Clock,Write,Addr)
 begin        

    if Write='1' then

        tmp_ram(conv_integer(Addr)) <= Data_in;         

    end if;   

end process;       

process(Clock,Read,Addr)
 begin          
    if Read='1' then

        Data_out <= tmp_ram(conv_integer(Addr));            

    end if;   

end process;

end behav;
banupriya
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  • How is this related to VHDL? It sounds more like a hardware related issue, related to some DDR memory, or similar. – Morten Zilmer Sep 23 '13 at 10:14
  • I have created a 256 byte capacity RAM programmatically using VHDL. I have added contents to that memory, I know the address of cells in the memory array but not able to find it's corresponding row and column number! – banupriya Sep 23 '13 at 10:38
  • Could you please show your VHDL code for the memory and fault detector entities? It will be it easier to give any advice if we can se the actual code. – rick Sep 23 '13 at 19:10
  • I have posted the code for creating a simple 256 byte RAM. After performing read and write operation in memory, I have injected faults in some addresses. For these faulty addresses, I have to get the row and column number – banupriya Sep 24 '13 at 09:07

1 Answers1

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Assuming you are referring to an SRAM, the manner in which rows and columns are ordered is specific to the actual hardware layout, and is generally not important for the VHDL code that uses the RAM (unless you are really interested in hand-optimizing power consumption for example). Typically some number of least significant bits refer to the column, and the most significant bits refer to the row. Thus if you know the number of rows and columns you can just split the address bits into row and column addresses, although this still assumes that the SRAM does not have some other layout internally.

If you code a RAM as an array in VHDL (letting the synthesis tool infer the RAM for you), you only code a one-dimensional array containing the number of words in the RAM. For example:

type ram_type is array(0 to g_DATA_DEPTH-1) of std_logic_vector(g_DATA_WIDTH-1 downto 0);

Letting g_DATA_DEPTH=1024, it is clear that the actual structure of the RAM is ambiguous: it could be 1x1024, 2x512, 4x256, etc.

The RAM is therefore best viewed as a one-dimensional array of words, rather than separating it into rows and columns.

zennehoy
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  • Yes, RAM is implemented as an array structure... But actual RAM structure is an array with rows and columns... Please look through the code posted along with my question... After performing read and write operation in memory, I have injected faults in some addresses. For these faulty addresses, I have to get the row and column number. – banupriya Sep 24 '13 at 09:06
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    @banupriya VHDL is a hardware description language, and you used it to describe a register-transfer-level implementation of a RAM. At this level, the RAM has a single column of words and 256 rows. Thus your address is equivalent to your row index, and your column index is 0. Without knowing the gate-level or transistor-level RAM structure that your code gets synthesized to, there is no way to know what address corresponds to what row or column in the physical hardware. Synthesizing your VHDL code maps it to hardware primitives for whatever synthesis target you have (FPGA, ASIC, ...)? – zennehoy Sep 24 '13 at 09:18
  • Got your point. Generally in hardware perspective a memory to be tested is organized as rows and columns. Faulty locations are identified using Built In Self Test concept. The row and column number corresponding to faulty locations should be obtained and fault list has to be created. My aim is to detect those faulty rows and columns, use an algorithm to generate repair solutions and perform Built In Self Repair in the Memory Under Test using the solution generated.How to model RAM programmatically so that it would contain n rows and columns? I am very new to VHDL language, so please guide me. – banupriya Sep 24 '13 at 09:41
  • @banupriya If you just want to model a RAM independently of a specific hardware implementation, you can simply choose how many rows and columns you want the RAM to have. Ignoring things like blocks etc., a fairly good approximation is to make the RAM square (`sqrt(g_DATA_DEPTH*g_DATA_WIDTH)` rows and columns). For your 256x8 bit RAM you could use 64 rows and 32 (4 words) columns. `addr(1 downto 0)` would then be your column index, `addr(7 downto 2)` your row index. – zennehoy Sep 24 '13 at 11:22