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Im getting this error in compiling this VHDL code with ModelSim: 

** Error: testVHDL_5.vhd(14): Cannot read output "z".
#   VHDL 2008 allows reading outputs.
#   This facility is enabled by compiling with -2008.

VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity gate_1 is
    port(
        a, b, c : in std_logic;
        x, z : out std_logic
        );
end gate_1;

architecture arch1 of gate_1 is 
begin -- rt1
    z <= b or c;
    x <= a and b and z;
end arch1;

testVHDL_5 is the name of my file. I know in the problem is that z cant be used in x. Can someone explain why and suggest a solution. Thanks.

Stelios Spector
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  • Does this answer your question? [VHDL: Unable to read output status](https://stackoverflow.com/questions/22120218/vhdl-unable-to-read-output-status) –  Dec 11 '19 at 13:20

2 Answers2

2

I know in the problem is that z cant be used in x.

Yes, that is what the error message says.

Can someone explain why

Because you can't read an output in VHDL in versions before 2008.

and suggest a solution.

Compile using the 2008 VHDL version.

And please do NOT use port names like like x and z. They are too easily confused with std_logic values of 'X' and 'Z'.

Oldfart
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    I can't tell that because I have no idea what you want the code to do. It seem a simple OR and an AND function. – Oldfart Dec 11 '19 at 11:52
2

You can use an internal signal to assign (b or c) and use that for calculating x.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity gate_1 is
  port(
    a, b, c : in  std_logic;
    x, z    : out std_logic
    );
end gate_1;

architecture arch1 of gate_1 is
  signal temp : std_logic;
begin 
  temp <= b or c;
  x    <= a and b and temp;
  z    <= temp;
end arch1;

You don't need to enable VHDL 2008 for this.

As @oldfart said, Please do not use x,z. Use meaningful names.

maximus
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  • IMO this is the better solution as using a port of mode `out` as an input is likely to confuse somebody in the future. I would however avoid using signal names like `temp`; perhaps something like `z_sig` or even `z_temp` would be better (as would not using `x` or `z` at all). – scary_jeff Dec 11 '19 at 13:17
  • Agree that. Moreover, looks like OP is unaware of the usage of internal signals. I never used/will never use `temp` as signal name. Something meaningful to the context. – maximus Dec 12 '19 at 08:44