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Questions tagged [vlsi]

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

In addition, VLSI Technology, Inc was a company which designed and manufactured custom and semi-custom ICs. The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose, California. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.

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Datapath on CPU and cycles

we have a Datapath from one CPU, such as following figure. if the next instruction address be in PC Register, how many clock cycle need to following word add instruction is fetched and executed? Memory is 10-bits and each instruction at least…
user4249446
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Time it takes to load data from prom

I'm working on multibooting of FPGA , I"m sending a sequence of commands and during the middle I need to load data from PROM memory. I am specifying the address from which the data should be loaded. SO my question is How many clock cycles does prom…
Akhil
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How can i catch error message from command line TCL

I'm writing script at tcl on ICC and trying to get error message while sending ran to sung-grid. For example, I have the below line. sh /usr/bin/xterm -e "cd DM ; mqsub -int -parallel 200 cal -cal -t 200 CAL_header | tee S.log ; touch .S_finished"…
user3835935
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Verilog FIFO code written with different styles..one not working and another not working.Can someone explain

I have written verilog code for fifo using fillcount to check as the means for checking if it is full or empty. There are 2 versions of the same code. One is whereI have a seprate always always block for reading,writing,empty /full ,fillcount,and…
mjaju
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wait on an untimed signal in VHDL testbench

I have written a simulation process that sets or changes signals sequentially as required, I use wait statements normally to wait certain time intervals or wait on signal assignments, but that is true only when I know when a signal should be coming,…
mewais
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Connecting a 4 bit shift register output to a 4 bit input in another module in Verilog

For our school project I am trying to use linear feedback shift register for pseudo-random number generation on hardware (seven segment). I have written the LFSR and seven segment module, however I have trouble connecting the two modules with each…
user3622555
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malformed statement in verilog

Hi i am using the folowing code to design a n-bit counter. Depending on the start and end i want to instantiate up or down counter. But i am getting "Malformed statement". Please help. module nbitUpCounter(startc,endc , clk,…
Dib
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Are there compiler directives for specifying the type of adder synthesized?

I haven't had any luck finding this on Google, so here goes: Has anyone heard of a design compiler directive to specify which type of adder is synthesized? I'm looking for something that would work somewhat like this: logic [7:0] a, b, c, d, e,…
tomocafe
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e Verification Language Compiler

Is there any free complier for Verisity's e Verification Language ?
joe
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Dealing with clock in Synopsys tetramax

I am using tetramax to measure the fault coverage of some test-benches. I am running the test-benches and dumping on a VCD file input and output of the core I want to test. The clock as well as the reset are already managed by my external…
Stefano
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Ready and valid

Does has any difference in Request and Valid signal for handshake protocol ? I am looking for the protocol which has request and valid both signals. Are any protocol used in VLSI filed ? does request and valid are same or different.
Charmi Toliya
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clarifications about katasuba algorithm

i'm investigating multiplication algorithms for a design im working on. I'm trying get an implementation of a 128 bit multiplier using the karasuba algorithm, however I'm not getting the results that I expect all the time, so I believe I'm still…
Rhysio Eren
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create_generated_clock -edges {1 5 9}, is asynchronous to its source?

I have these clocks defined. When I add multicycle constraint on the registers that form timing paths from clk_1_gated to clk_250, the multicycle constraints are ignored. I was wondering if defining: create_generated_clock -edges is creating an…
Tlalit
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Truncated ternary multipliers ulp error calculation

the following paper provides some insides about truncated ternary multipliers: https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-cdt.2013.0133 , I understand the concept explained here in general but there is one detail related to the…
Rhysio Eren
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STA of 2 clocks with the same frequency

Imagine a design has 2 input clocks. They have the "same" nominal frequency but originate from 2 different sources and therefore are asynchronous to each other. The clocks are defined as follows: create_clock -name {clock_a} -period 10.000 -waveform…
shaiko
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