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we have a Datapath from one CPU, such as following figure. if the next instruction address be in PC Register,

how many clock cycle need to following word add instruction is fetched and executed?

Memory is 10-bits and each instruction at least is 2-words. all register is 10-bits and has INC (increment), CLR (clear), LD(load) instructions. Addr means direct addressing. instruction will work on 10-bits word:

Wadd (src1), (src2), (dst)

enter image description here

My instructor solve it that it's on 15 clock cycle. any hint or idea, how this will be calculated?

Edit:

My try * but i'm not sure, my try is True or False:

enter image description here

1 Answers1

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Your solution doesn't quite work as you move the PC once too many times, meaning you are loading the destination pointer as the source 2 pointer (in step 5, you shouldn't increment PC again). I didn't notice any other errors in your solution, however I was able to find one that is faster:

[UPDATE: Apparently there is an IR assumed to be in the processor; so we will assume IR can be loaded from DR]

Get Op Code

Step 1: AR <- PC

Step 2: DR <- M[AR]; PC++; AR++

Step 3: IR <- DR; DR <- M[AR]

Step 4: Decode(IR)

Get SRC1

Step 5: AR <- DR; PC++

Step 6: DR <- M[AR]; AR <- PC

Get SRC2 (SRC1 to AC)

Step 7: AC <- DR; DR <- M[AR]; PC++

Step 8: AR <- DR

Step 9: DR <- M[AR]; AR <- PC

Add and get DEST

Step 10: AC <- AC + DR; DR <- M[AR]

Put answer in DEST (The separate ones are if we want to keep going to the next instruction)

Step 11: AR <- DR; DR <- AC PC++

Step 12: M[AR] <- DR AR <- PC

[UPDATE2: As there seems to be a random requirement to take 15 cycles; here is a 15 cycle solution... Note that the 12 cycle is ideal, and you should discuss it with your TA/Professor]

Get Op Code

Step 1: AR <- PC

Step 2: DR <- M[AR]; PC++; AR++

Step 3: IR <- DR

Step 4: DR <- M[AR]

Step 5: Decode(IR)

Get SRC1

Step 6: AR <- DR; PC++

Step 7: DR <- M[AR]

Step 8: AR <- PC

Get SRC2 (SRC1 to AC)

Step 9: AC <- DR

Step 10: DR <- M[AR]; PC++

Step 11: AR <- DR

Step 12: DR <- M[AR]; AR <- PC

Add and get DEST

Step 13: AC <- AC + DR; DR <- M[AR]

Put answer in DEST (The separate ones are if we want to keep going to the next instruction)

Step 14: AR <- DR; DR <- AC PC++

Step 15: M[AR] <- DR AR <- PC

Unn
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  • i calculate 14, the closest to right answer (15), Pc -> ar Pc(src1) -> ar mem(src1) -> dr dr -> ar mem -> dr dr -> ac mem(src2) -> dr dr -> ar mem -> dr dr + ac -> ac dest -> dr dr -> ar ac - > dr dr -> mem –  Feb 19 '15 at 09:56
  • Do you care about reducing the cycles or the number of register transfers? In my solution given in the answer, it takes 11 cycles to complete the operation (many of these steps have more than one transfer per cycle). If you wish to reduce the number of transfers, there might be a better solution – Unn Feb 19 '15 at 17:31
  • Dear @Unn, the selected choice of this question is (15), (10) or (20), that 15 is selected by TA. would you please again inspect my question ? –  Feb 19 '15 at 17:37
  • He say, we need 8 clock to transfer 4 word instruction to IR, then 7 Clock need to AC+DR and send it to memory. he says all processor has IR register and not need to show in datapath. –  Feb 19 '15 at 17:43
  • @user4249446 While almost all processors do have an instruction register, it is not appropriate to assume structures (registers or logic) which are not present in the datapath or description of the processor (The only structure I had to assume was decode logic and the controlpath logic/FSM which may or may not be shown; an explicit IR connected to the output of the memory somehow SHOULD be in that image you provided, I cannot know how that register which sounds like its 40bits? is connected to the others in the datapath). In order to fetch, decode and execute WADD, it could take 11 or more. – Unn Feb 19 '15 at 18:05
  • No, there aren't 40-bit register, i think we should divide our work in 4 part. –  Feb 19 '15 at 18:07
  • Long answer short, ignoring any class-specific restrictions or information not provided in your answer (as I dont know them), given the question what is the minimum number of cycles it takes to do a WADD (which is what it sounds like it wants), the answer is 11 unless someone else finds a more optimum solution. – Unn Feb 19 '15 at 18:08
  • Let us [continue this discussion in chat](http://chat.stackoverflow.com/rooms/71284/discussion-between-user4249446-and-unn). –  Feb 19 '15 at 18:10
  • As we might now be in a "guess-what-the-TA/Professor-wants" rather than working through what the controlpath would have to do to make the given datapath preform a WADD, Im not sure I can help more than what Ive given you. Ill need to know more to guess at the TAs answer; and he/she should explain to you why your answer of 14 cycles and my answer of 11 cycles doesnt work. – Unn Feb 19 '15 at 18:13
  • are u there? i inspect it. –  Feb 23 '15 at 18:54
  • I am in the discussion (chat) if you need something :) – Unn Feb 23 '15 at 18:56
  • can we continue in chat ? –  Feb 23 '15 at 18:57