I have these clocks defined. When I add multicycle constraint on the registers that form timing paths from clk_1_gated to clk_250, the multicycle constraints are ignored. I was wondering if defining: create_generated_clock -edges is creating an asynchronous clock to the source clock clk_1_gated.
(If I do, create_generated_clock -divide_by 4 , instead of create_generated_clock -edges, the multicycle constraints works ok.)
SDC:
create_clock [get_ports clk_1] -name clk_1 -period 1 -waveform {0 0.5}
create_generated_clock -name clk_1_gated -source clk_1 -edges {1 2 3} [get_pins {i_dig/CGT/Q}]
create_generated_clock -name clk_250 -source i_dig/CGT/Q -edges {1 5 9} [get_pins {i_dig/clk_250_gated/CGT/Q}]
set_multicycle_path 4 -from [get_pins {i_dig/i_dig_coding/i_ff0/q[21]}] -to [get_ports ff_sel[21]]
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