Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

system-verilog system-verilog-assertions system-verilog-dpi uvm vpi icarus iverilog verilator

6035 questions

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1 answer

Passing a 256-bit wire to a C function through the Verilog VPI

I have a 256-bit value in Verilog: reg [255:0] val; I want to define a system task $foo that calls out to external C using the VPI, so I can call $foo like this: $foo(val); Now, in the C definition for the function 'foo', I cannot simply read the…

c verilog

asked Feb 17 '10 at 17:16

pheaver

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Verilog: value(s) does not match array range, simulation mismatch

The following code synthesizes and simulates correctly as far as I can tell, but XST is still giving the following warning: value(s) does not match array range, simulation mismatch. Is there something I'm missing? Tool used: Xilinx ISE Project…

verilog xilinx hdl

asked Mar 06 '14 at 05:33

verigolfer

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4 answers

Verilog/VHDL - How to avoid resetting data registers within a single always block?

I like to avoid resetting data registers that don't need to be reset. For example, when streaming data through pipeline stages, if each stage has a valid bit, there is no need to reset the data registers. (I believe this eases routing and timing on…

asynchronous vhdl verilog reset synchronous

asked Jan 31 '14 at 00:39

mksuth

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3 answers

Verilog ** Notation

What does ** mean in verilog? I have the following logic provided for a testbench localparam NUM_INPUT_BITS = 1; localparam NUM_OUTPUT_BITS = NUM_INPUT_BITS + 1; localparam MAX_OUTPUT_BIT = NUM_OUTPUT_BITS - 1; localparam…

verilog system-verilog

asked Jan 23 '14 at 14:54

Nathan Tornquist

6,468
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3 answers

Verilog two-way handshaking example

I'm finishing up a project and a requirement is two-way handshaking between functional units inside our processor. I know what it is but is there any 'standard' or a good simple example of it? Only thing I can think of between two units, when…

verilog processor cpu-architecture

asked Dec 17 '13 at 21:57

Zachary Karpinski

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2 answers

What to use to compile and simulate Verilog programs on Mac OS X 10.6.8?

I am required to simulate Verilog programs as part of my syllabus. But, my college uses Xilinx ISE, and it isn't available for Mac. So please help me out with the best software and also some detailed steps on how to install and use them.

macos verilog hdl

asked Oct 14 '13 at 21:37

BharathYes

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2 answers

SystemVerilog program block vs. traditional testbench

Are there any features of SV that a program block offers that can't be duplicated with other methods? The less concrete version of this question is: should I bother with program blocks for verification? I'm moving from an environment where we were…

unit-testing testing verilog system-verilog

asked Aug 23 '13 at 15:03

dan

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2 answers

Verilog access specific bits

I have problem in accessing 32 most significant and 32 least significant bits in Verilog. I have written the following code but I get the error "Illegal part-select expression" The point here is that I don't have access to a 64 bit register. Could…

bit-manipulation verilog

asked May 09 '13 at 18:02

farzin

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1 answer

How to pass array structure between two verilog modules

I am trying to pass a array structure as reg [0:31]instructionmem[0:31] between two modules. I coded it as follows : Module No 1: module module1(instructionmem); output reg [0:31]instructionmem[0:31]; …

module parameter-passing verilog

asked May 04 '13 at 01:26

Nilesh Agrawal

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1 answer

What is "gate count" in synthesis result and how to calculate

I'm synthesizing my design with design compiler and have some comparison with another design (as a evaluation in my report). The Synopsys's tool can easily report the area with command but in all paper I've read care about gate count. My quiz is…

vhdl verilog area synthesis

asked Feb 12 '13 at 14:38

Khanh N. Dang

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3 answers

How to implement a (pseudo) hardware random number generator

How do you implement a hardware random number generator in an HDL (verilog)? What options need to be considered? This question is following the self-answer format. Addition answers and updates are encouraged.

random verilog hdl

asked Jan 24 '13 at 09:27

Morgan

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Arithmetic shift acts as a logical shift, regardless of the signed variable

I've got a register declared as so: logic signed [15:0][2:0][15:0] registers; When I place a 2's compliment number into the array and arithmetically shift the number, it logical shifts instead: registers[0][0] =…

verilog bit-shift system-verilog

asked Jan 07 '13 at 13:37

user1567095

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2 answers

Is there something like LINE in Verilog?

I am new to Verilog but have been a C programmer for years which makes me dangerous. I'm doing some Verilog for a class. I'd like to use C assert() style testing in my simulation code. https://en.wikipedia.org/wiki/Assert.h We aren't using System…

verilog system-verilog

asked Oct 13 '12 at 18:32

David Poole

3,432
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2 answers

Why is my D Flip Flop not waiting for the positive edge of the clock?

As I have known, D flipflop samples its input value at every positive edge of the clock. Thus, it will produce a 1 cycle delay. Right? But why does my D flip flop does not produce a 1 cycle delay? module flipflop( input clk, …

verilog

asked Jul 26 '12 at 15:01

e19293001

2,783
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2 answers

better way of coding a D flip-flop

Recently, I had seen some D flip-flop RTL code in verilog like this: module d_ff( input d, input clk, input reset, input we, output q ); always @(posedge clk) begin …

verilog

asked Jun 13 '12 at 03:10

e19293001

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