Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

From Wikipedia:

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

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What is the point of a "plain" begin-end block?

I'm reading some third party Verilog, and found this: function [31:0] factorial; input [3:0] operand; reg [3:0] index; begin factorial = operand ? 1 : 0; for(index = 2; index <= operand; index = index + 1) …
Randomblue
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What does the term "Verilog Synthesis" mean?

When someone asks you if you've ever done any verilog synthesis, what does that really mean? Does that mean writing out the code, simulation, downloading the code to the actual hardware, or what? I read it online but they just said it's the process…
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Assign ASCII character to wire in Verilog

I understand that you can declare a string in a Verilog test bench as follows: reg [8*14:1] string_value; initial string_value = "Hello, World!"; I can then do things with this string, like use $display in a test bench to display it. I…
Kevin Vermeer
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Alternatives to $readmemh in Verilog

I'm trying to load values from a file into a two-dimensional array like this. reg [31:0] RAM[63:0]; initial $readmemh("memory.dat",RAM); What are the alternatives? If I wanted to hardcode the values stored in the memory instead, what's the…
node ninja
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Proper way for signal edge detection in Verilog

I want to detect a rising edge of a signal from a flip-flop AA to BB +----+ A ----------------| |----- OUT +----+ | BB | B ----| |------|> | | AA | +----+ clk ----|> | …
e19293001
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Exporting tasks to 'C using DPI

I have an verilog based test-bench, interfaced to 'C source using DPI. Now using DPI I am planning to write my whole firmware. To do this I need 3 things Register Read Register Write Interrupt handler As I understand, register reads and writes are…
Alphaneo
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Difference between 1 and 1'b1 in Verilog

What is the difference between just giving 1 and giving 1'b1 in verilog code?
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converting a wire value to an integer in verilog

I want to convert the data in a wire to an integer. For example: wire [2:0] w = 3'b101; I want a method that converts this to '5' and stores it in an integer. How can I do that in a better way than this: j=1; for(i=0; i<=2; i=i+1) begin …
Brahadeesh
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Is recursive instantiation possible in Verilog?

Some problems lead themselves to a recursive solution. Is recursive instantiation possible in Verilog? Is it possible for a module to instantiate itself?
Matthew Taylor
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Have the errors in "HDL Chip Design" by Douglas Smith ever been corrected?

My copy of "HDL Chip Design" by Douglas Smith is the ninth printing, July 2001. The book systematically makes the error of using blocking assignments for synchronous communication, which results in nondeterministic code. Non-blocking assignments…
Jan Decaluwe
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Do any open source, complete system verilog grammars exist?

Are there any grammars for system Verilog that are open source? I'm looking for System Verilog, not plain Verilog grammars.
Ross Rogers
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BCD Adder in Verilog

I am trying to write a BCD Adder in Verilog, but I am having trouble with one of the modules. Specifically, the adder that takes two BCD digits and adds them. So, the idea is if the sum of the two digits is less than or equal to nine, then it is…
DemonicImpact
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How do I use set LVDS mode on Lattice ICE40 pins using ICESTORM tools

I have a Lattice ICE40_8K breakout board and would like to know how to setup a pin pair as LVDS mode inputs. If setting up as normal single pins is done thus: SB_IO #(.PIN_TYPE(6'b0000_00)) _io ( .PACKAGE_PIN(pin), .INPUT_CLK(clk), …
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What is the difference between using an initial block vs initializing a reg variable in systemverilog?

What is the difference between the following two examples with regards to simulation? A) reg a; initial a = 1'b0; and B) reg a = 1'b0; Is it different for logic variables?
supernun
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Why should an HDL simulation (from source code) have access to the simulator's API?

This is a question inspired by this question and answer pair: call questa sim commands from SystemVerilog test bench The questions asks how Verilog code could control the executing simulator (QuestaSim). I saw similar questions and approaches for…
Paebbels
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