Stack Overflow
Stack Overflow

Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

From Wikipedia:

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

6035 questions
25
votes
7 answers

How to write a linter?

In my day job I, and others on my team write a lot of hardware models in Verilog-AMS, a language supported primarily by commercial vendors and a few opensource simulator projects. One thing that would make supporting each others code more helpful…
jbdavid
  • 602
  • 1
  • 7
  • 9
22
votes
4 answers

Better way of coding a RAM in Verilog

Which code is better in writing a RAM? assigning data_out inside always block: module memory( output reg [7:0] data_out, input [7:0] address, input [7:0] data_in, input write_enable, input clk ); reg [7:0] memory [0:255]; …
e19293001
  • 2,783
  • 9
  • 42
  • 54
22
votes
6 answers

Verilog generate/genvar in an always block

I'm trying to get a module to pass the syntax check in ISE 12.4, and it gives me an error I don't understand. First a code snippet: parameter ROWBITS = 4; reg [ROWBITS-1:0] temp; genvar c; generate always @(posedge sysclk) begin for (c…
user1684538
  • 221
  • 1
  • 2
  • 3
21
votes
6 answers

Verilog automatic task

What does it mean if a task is declared with the automatic keyword in Verilog? task automatic do_things; input [31:0] number_of_things; reg [31:0] tmp_thing; begin // ... end endtask; Note: This question is mostly because I'm curious if…
cdleary
  • 69,512
  • 53
  • 163
  • 191
21
votes
2 answers

Using parameters to create constant in verilog

I want to take in a parameter and assign a number of zeroes equal to the paramter to a constant, and use this constant for comparison. how do I do it ? For example, say parameter is 3, I want to create a constant n=3'b000; and use this n in…
Floose
  • 525
  • 2
  • 7
  • 15
21
votes
2 answers

What is the difference between Verilog ! and ~?

So it ended up that the bug that had kept me on for days, was a section of code that should have evaluated to False evaluating to True. My initial code went something like: if(~x && ~y) begin //do stuff end i.e. If x is NOT ONE and y is NOT ONE…
SleepingSpider
  • 1,168
  • 4
  • 19
  • 35
20
votes
2 answers

What is the difference between = and <= in Verilog?

What is the difference between = and <= in this code? Also, how do I print the value of data? module always_example(); reg clk,reset,enable,q_in,data; always @ (posedge clk) if (reset) begin data <= 0; end else if (enable) begin data…
Hayder Al-Amily
  • 329
  • 1
  • 4
  • 9
19
votes
2 answers

How to define and initialize a vector containing only ones in Verilog?

If I want to declare a 128 bit vector of all ones, which one of these methods is always correct? wire [127:0] mywire; assign mywire = 128'b1; assign mywire = {128{1'b1}}; assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
Veridian
  • 3,531
  • 12
  • 46
  • 80
18
votes
2 answers

How can I assign a "don't care" value to an output in a combinational module in Verilog

Imagine we want to describe a combinational circuit that satisfy the following truth table: a b | s0 s1 s2 s3 ----------------- 0 0 | 1 d d d 0 1 | 0 1 d d 1 0 | 0 0 1 d 1 1 | 0 0 0 1 (where d stands for "don't care" value, that is,…
mcleod_ideafix
  • 11,128
  • 2
  • 24
  • 32
18
votes
3 answers

Verilog: How to instantiate a module

If I have a Verilog module 'top' and a verilog module 'subcomponent' how do I instantiate subcomponent in top? top: module top( input clk, input rst_n, input enable, input [9:0] data_rx_1, input [9:0]…
Morgan
  • 19,934
  • 8
  • 58
  • 84
18
votes
12 answers

Division in verilog

I am teaching myself verilog. The book I am following stated in the introduction chapters that to perform division we use the '/' operator or '%' operator. In later chapters it's saying that division is too complex for verilog and cannot be…
StuckInPhDNoMore
  • 2,507
  • 4
  • 41
  • 73
17
votes
2 answers

$size, $bits, verilog

What is the difference between $size and $bits operator in verilog.? if I've variables, [9:0]a,[6:0]b,[31:0]c. c <= [($size(a)+$size(b)-1]-:$bits(b)]; What will be the output at 'c' from the above expression?
Suhas
  • 319
  • 2
  • 5
  • 14
16
votes
1 answer

What is the function of $readmemh and $writememh in Verilog?

I have been looking at some Verilog testbench code that heavily uses $readmemh and $writememh. I have a vague understanding that these functions basically read to and write from memory. What is their specific function and how do they work?
Alphaneo
  • 12,079
  • 22
  • 71
  • 89
16
votes
1 answer

Assigning values in Verilog: difference between assign, <= and =

I have just started learning Verilog and I've seen these three lines from different sources. I am confused about the difference between the three: c <= a&b; assign c = ~a; c = 1'b0; These lines seem to assign a value to c but what's the…
dringx
  • 163
  • 1
  • 1
  • 5
16
votes
1 answer

Include a module in verilog

I want to include a verilog module into another file. How do I include it in the code and how do I compile the code to include the header file? Is it like in c?
user1730250
  • 582
  • 2
  • 9
  • 26
1
2
3
…
99 100