7

The following code synthesizes and simulates correctly as far as I can tell, but XST is still giving the following warning: value(s) does not match array range, simulation mismatch. Is there something I'm missing?

Tool used: Xilinx ISE Project Navigator (synthesizer:XST) FPGA: SPARTAN 3E

module error_example(
    input [47:0] data,
    input [2:0] sel,
    output [5:0] data_out
);

   assign data_out = data[sel*6 +: 6];

endmodule

WARNING:Xst:790 - "error_example.v" line 8: Index value(s) does not match array range, simulation mismatch.

Like I said, this works and I've done the math:

sel can have values from 0 to 7,

if sel is 0, then data_out = data[5:0] ...

if sel is 7, then data_out = data[47:42]

Should I do something differently here? Is this a bug in XST?

nguthrie
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verigolfer
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  • @nguthrie I'm pretty sure it was correct before your edits. If I wanted `data_out = data[5:0]` when `sel = 0` then I would have wrote `assign data_out = data[6*sel+5 -: 6]`. It was much more convenient to use little endian format when I included this as part of a much larger module. – verigolfer Mar 06 '14 at 19:05
  • See section 11.5.1 of the spec. The first example shows a vector defined as [31:0] and then does a part select with [0 +: 8] and the result is bits [7:0]. I haven't used this feature very often since it is quite confusing. – nguthrie Mar 06 '14 at 19:36
  • Spec I am referring to is 1800-2012: http://standards.ieee.org/getieee/1800/download/1800-2012.pdf hopefully things didn't change from the verilog spec. – nguthrie Mar 06 '14 at 19:40
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    Your original example had the data vector defines [lsb:msb] but you changed it to [msb:lsb] with your first edit. Hence the difference. – nguthrie Mar 06 '14 at 19:45
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    First hit on google says this message is sometimes invalid: http://forums.xilinx.com/t5/Synthesis/I-don-t-understand-quot-Xst-790-Index-value-s-does-not-match/td-p/36347 – nguthrie Mar 06 '14 at 19:57
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    @nguthrie, good catch with the `[lsb:msb]` that does change the behavior of `+:`. `+:` means bits to the left, not ascending bits. – Greg Mar 06 '14 at 20:55

1 Answers1

5

I have created the example on EDAplayground, which runs without warning.

I would not normally use widths with parameters and if you do you might want to be consistent with the reg definitions.

Try:

  1. parameter data = 48'h123456789ABC;
  2. parameter [47:0] data = 48'h123456789ABC;

I do not think I have used parameters this way before but declaring a constant reg implies the same logic, which might avoid the warning.

  1. reg [47:0] data = 48'h123456789ABC;

NB: It is good practise to use upper case for constants (parameter,localparam).

Alternatively convert to a case statement:

always @* begin
  case (sel)
    3'd0: data_out = 6'dx;
    3'd1: data_out = 6'dx;
    // ...
    default :  data_out = 6'd0;
  endcase
end
Morgan
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  • Regardless of the parameter, the warning still exists.. Edited my question. – verigolfer Mar 06 '14 at 07:59
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    I would raise the issue with your tool vendor, the `+:6` should guarantee the widths are the same. However this is a relatively new feature (2005) and support takes some time to propagate to all tools. – Morgan Mar 06 '14 at 09:17
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    Actually, the `+:` is relatively old. It was introduced in IEEE Std 1364-2001 section 4.2.1 _Vector bit-select and part-select addressing_ – Greg Mar 06 '14 at 17:26
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    @Greg Your correct, I should double check my facts before stating them. [Part 15 Of Sunburst Verilog 2001](http://www.sutherland-hdl.com/online_verilog_ref_guide/verilog_2001_ref_guide.pdf) also covers it quite well. – Morgan Mar 06 '14 at 18:38
  • @Morgan I like your answer but it doesn't completely address my question. My data was really 768 bits wide (reduced for the example) and I didn't want to write 128 different cases. – verigolfer Mar 06 '14 at 19:09
  • @verigolfer, do you get the same warning with `data` being 48 bits wide? When the `data` is 768 wide, `sel` is 128 bits and `data_out` is 6 bits? If the answers are no and yes respectively, then the mux is too big for SXT to handle. In this case break the big mux into more manageable muxes such as several 32-to-1 muxes. – Greg Mar 06 '14 at 19:44
  • @ Greg I did some experimenting and the message only happens when the data width is not a power of 2. I'm fairly convinced it's a bug with the synthesis tool, but Xilinx hasn't responded to my email about it. – verigolfer Mar 07 '14 at 02:00