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Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

From Wikipedia:

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

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Define multi-character parentheses in Emacs

In Verilog you enclose code blocks between the words 'begin' and 'end' like this: if(foo) begin x <= 1'b0; y <= 1'b0; end else begin x <= x_d; y <= y_d; end Is there any way to set begin and end as parentheses in Emacs, so that you can…
Katy Montgomerie
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Verilog Best Practice - Incrementing a variable

I'm by no means a Verilog expert, and I was wondering if someone knew which of these ways to increment a value was better. Sorry if this is too simple a question. Way A: In a combinational logic block, probably in a state machine: //some…
Cory G.
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Specifying variable range in Verilog using for loop

I am trying to write this code: for (i = 0; i <= CONST - 1'b1; i = i + 1'b1) begin : loop_inst if (i < 3) begin if (changed[i] & !done_q[i]) …
typon
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Passing hierarchy into a Verilog module

I have a "watcher" module that is currently using global hierarchies inside it. I need to instantiate a second instance of this with a second global hierarchy. Currently: module watcher; wire sig = `HIER.sig; wire bar =…
pdq
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Is there a reason to initialize (not reset) signals in VHDL and Verilog?

I have never initialized signals. That way any signal missing a reset or assignment would be unknown or initialized. In some reference code they have initialization. This defeats what I wish. Also since intialization isn't synthesizable, there could…
Brian Carlton
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case statement with multiple cases doing same operation

I need to use a case statement with the control signal being 4 bits. I have multiple cases of those 4 bits doing the same operation, how do I make the code more concise? For ex: casez (fbe) //fbe is defined as logic [3:0] fbe; 4'b0000: begin …
Gaurav Gupte
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Arrays of interface instances in SystemVerilog with parametrized number of elements

I'm using SystemVerilog for synthesis. I fought with the fact that arrays of interfaces are not really arrays in SystemVerilog and the index has to be a constant value, but got over it using at lot of boilerplate generate for and assign statements…
apriori
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How to remove I/O port declarations using regexp in verilog mode

I'm trying to instantiate abc_d module and i don't want all of its ports to be declared as I/O ports in abc top module. I want to exclude ex_out_port to be declared as output port. module…
user43102
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How to write to inout port and read from inout port of the same module?

This is not about actually creating a verilog module with inout ports. There are tons of posts I've found about that. What I am stuck on is, if I have a blackbox module with an inout port, let's says it's defined like module blackbox(inout a, in b,…
FatherOfNations
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Assign integer to reg in Verilog

I have problems with this Verilog code. Basically, it won't let me do the Y = 3'di statement. Basically, I want Y to equal i. I am pretty sure the problem is the i. So, is there a way to do this in Verilog? Also, W is an input with 8 bits (in other…
DemonicImpact
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Is it possible to create a simulation waveform from yosys output

I've found simulating using iverilog to be a less than suitable method, I can simulate designs that won't synthesise and conversely designs that will not only synthesize but also work as intended on physical hardware, won't synthesise with iverilog…
Chris Camacho
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When exactly to use "assign" keyword and when to use "<=" operators?

I'm learning verilog, I have read some tutorials but i'm a bit confused about this: When and why to use the "assign" keyword and when and why use the "<=" operators. In what context? It is clear for me the difference between "<=" and "=", being…
sujeto1
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Printing packed structs in System Verilog

I have a packed struct defined as shown below typedef struct packed { logic bit1; logic [7:0] byte1; } MyPackedStruct; MyPackedStruct myPackedStruct; Is there any SV built in function that I could use to print the structures similar to…
Vissu
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Verilog signed vs unsigned samples and first

Assuming I have a register reg [15:0] my_reg, which contains a 16-bit signed sample: How do I convert the sample from signed to unsigned? I have read this Wikipedia article, and am aware of the 2-bit complement for signed numbers, but how do I…
titus.andronicus
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Prevent systemverilog compilation if certain macro isn't set

I am writing a systemverilog module and I need to make sure that a certain macro is set to allow compilation to proceed. I have tried the below, but it simply gives the syntax error "unexpected SYSTEM_IDENTIFIER" $fatal. I know that does technically…
miles.sherman
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