Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

system-verilog system-verilog-assertions system-verilog-dpi uvm vpi icarus iverilog verilator

6035 questions

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3 answers

Verilog question mark (?) operator

I'm trying to translate a Verilog program into VHDL and have stumbled across a statement where a question mark (?) operator is used in the Verilog program. The following is the Verilog code; 1 module music(clk, speaker); 2 input clk; 3 output…

operators vhdl verilog

asked Sep 09 '12 at 02:48

Triple777er

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4 answers

The difference between x and z

While reading the syntax of Verilog, I came across the four logic values: 0 1 x z. After searching the web, seeking to find the difference between x and z, I found only that x is unknown value and z is high impedance (tristate). I think that I…

verilog

asked Apr 23 '18 at 17:41

verrrilog

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2 answers

Testing FPGA Designs at Different Levels

Various aspects of test strategies for FPGAs have been discussed here on SO but I can't find that the following question has been asked/discussed/answered: At what levels should you simulate your FPGA design and what do you verify at each level? If…

testing vhdl verilog fpga

asked Sep 03 '15 at 17:05

lasplund

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3 answers

Can Verilog variables be given local scope to an always block?

I sometimes find it useful to use blocking assignments for "local variables" inside clocked always blocks. This can help cut down on repeated code. To avoid accidentally using the same variable in a different always block (which can be…

scope verilog system-verilog

asked Sep 15 '14 at 22:03

mksuth

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3 answers

' << ' operator in verilog

i have a verilog code in which there is a line as follows: parameter ADDR_WIDTH = 8 ; parameter RAM_DEPTH = 1 << ADDR_WIDTH; here what will be stored in RAM_DEPTH and what does the << operator do here.

operator-keyword verilog

asked Jul 17 '13 at 04:43

biren.K

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3 answers

What does always block @(*) means?

If I write the following code: module POLY(CLK,RESET_n,IN_VALID,IN,OUT_VALID,OUT); input CLK,RESET_n,IN_VALID; input [ 3:0] IN; output OUT_VALID; output [12:0] OUT; and then use it: always @(*) begin ......... end Does it mean…

verilog

asked Mar 16 '13 at 13:57

Jason

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3
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2 answers

Verilog equivalent of "wait until ... for ..."?

In a Verilog testbench, I'm trying to code the following behavior: Wait until an event occurs (rising / falling edge) for a maximum time, i.e. an equivalent of the VHDL instruction: wait until for ; which has the following…

vhdl verilog

asked Sep 11 '12 at 13:01

Mousstix

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3 answers

How can I separate long statements into lines in Verilog

For example, I have a single long statement: $display("input_data: %x, output_data: %x, result: %x", input_data, output_data, result); How can I make it into single…

verilog system-verilog

asked Jul 17 '12 at 11:42

e19293001

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4 answers

What's included in a Verilog always @* sensitivity list?

I'm a bit confused about what is considered an input when you use the wildcard @* in an always block sensitivity list. For instance, in the following example, which signals are interpreted as inputs that cause the always block to be…

verilog system-verilog digital-logic

asked Mar 11 '12 at 21:27

Frank Dejay

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2 answers

Printing signed integer value stored in a variable of type reg

How do I print a signed integer value stored in an 8-bit register declared as: reg [7:0] acc; Using: $display("acc : %d", acc) It prints the unsigned value. What's the correct syntax for the $display function?

verilog system-verilog xilinx

asked Feb 17 '12 at 07:56

Nullpoet

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1 answer

How to generate schematic file from verilog source in Xilinx

What I'm doing I started playing around with Xilinx ISE Design Suite and wrote simple Arithmetical Logic Units in verilog. Using verilog Unit Under Tests to create input and output signals for ISim, I verified, that the code works just as I want…

verilog xilinx

asked Apr 20 '11 at 17:38

Margus

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5 answers

Logarithm in Verilog

I've a statement in verilog looking like integer level = log(N) (Where N is a parameter and level is to be determined) But I understand I cannot do complex math statements in verilog, so I'm wondering if there is an alternative solution to the above…

verilog logarithm

asked Apr 09 '11 at 00:55

Max Eastman

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9 answers

Finding the next in round-robin scheduling by bit twiddling

Consider the following problem. You have a bit-string that represents the current scheduled slave in one-hot encoding. For example, "00000100" (with the leftmost bit being #7 and rightmost #0) means that slave #2 is scheduled. Now, I want to pick…

algorithm bit-manipulation verilog vhdl

asked Jan 26 '09 at 16:31

Eli Bendersky

263,248
89
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3 answers

Prefered syntax for verilog module declaration

I am relatively new to FPGAs, and I am looking for some guidance for modern best practice regarding the declaration of modules in Verilog. I have seen two ways of declaring a module in verilog. The first reminds me of Traditional C, such as the…

syntax verilog

asked Aug 24 '16 at 06:41

Damien

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4 answers

How to initialize contents of inferred Block RAM (BRAM) in Verilog

I am having trouble initializing the contents of an inferred ram in Verilog. The code for the ram is as below: module ram( input clock, // System clock input we, // When high RAM sets data in input lines to given address …

verilog fpga xilinx vivado

asked Apr 13 '16 at 22:15

Paulo C

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