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Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

From Wikipedia:

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

6035 questions
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Error: "(vlog-2110) Illegal reference to net"

I have a simple FIFO code in SystemVerilog. I get several vlog-2110 illegal reference to net error messages. My error messages are followed by my code. Error messages: vlog -work work -sv -stats=none C:/Users/Single_FIFO.sv Model Technology…
SSadh
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VHDL: Is there a convenient way to assign ascii values to std_logic_vector?

In verilog, I can assign a string to a vector like: wire [39:0] hello; assign hello = "hello"; In VHDL, I'm having difficulty finding a method like this: SIGNAL hello : OUT std_logic_vector (39 DOWNTO 0); ... hello <= "hello"; I've been…
N8TRO
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Width independent functions

Is it possible to write a function that can detect the input data width automatically? For example, consider the parity function below: function parity; input [31:0] data; parity = ^ data; endfunction When parity(data) is called, the input…
Ari
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$display in Verilog and printf in C

As you know in Verilog has $display,$strobe and $monitor those used to display text on the screen. And in C has printf to display text on screen also. My question is how can I use one of them ($display,$strobe,$monitor) like printf in C? a:…
Tuyen Khuc
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Triggering signal on both edges of the clock

Design requires a signal to be activated at specific circumstance on rising edge of the clock, and deactivated at another circumstance on falling edge of clock. Here's what I think: always@(posedge CLK) begin signal1 <= 1'b0; // reset flag …
Anonymous
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Configure ModelSim simulation to display text

Can I make ModelSim simulation to display text (rather than a numeric value) on a signal? I have a couple of state-machine states say, localparam S_IDLE = 2'b00; localparam S_START = 2'b01; localparam S_STOP = 2'b10; Is there a way to display…
SleepingSpider
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What is always followed by #(...) pound mean in Verilog?

In a simple clock generator example, I see the following code: always #(cycle/2) clk ~= clk; I've seen always @(*) before but not pound (#). I tried to find it in the documentation, but all I could find was some reference to "real-valued ports"…
weiy
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Use of forever and always statements

Both the following codes generate a clock. I need to know if there is any use of forever loop other than clock generation? I have only come across forever in clock generation. If it only serves this purpose, isn't it useless? initial begin clk =…
chitranna
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What is the difference between structural Verilog and behavioural Verilog?

As in the title, what are the main differences between structural and behavioural Verilog?
user2219586
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Way to initialize synthesizable 2D array with constant values in Verilog

in VHDL, I can easily do this: constant cmdbytes : bytearray(0 to Total) := (x"05", x"00", x...}; I want synthesizable constants so that when the FPGA starts, this array has the data I supplied. These registers are wired to VCC or ground…
Hai Bi
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Fast, small area and low latency partial sorting algorithm

I'm looking for a fast way to do a partial sort of 81 numbers - Ideally I'm looking to extract the lowest 16 values (its not necessary for the 16 to be in the absolutely correct order). The target for this is dedicated hardware in an FPGA - so this…
trican
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always @* block with a single non-blocking assignment - good, bad or irrelevant?

The general rule of thumb mentioned in all of books I have read so far is that you have to use non-blocking assignments in always blocks that are driven by the raising or falling edge of the clock. On a contrary, blocking assignments must be used…
user405725
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What does "net" stand for in Verilog?

I'm just starting to learn Verilog. As I understand, Verilog has net datatypes. What does net stand for?
Randomblue
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Verilog Barrel Shifter

I want to create a 64-bit barrel shifter in verilog (rotate right for now). I want to know if there is a way to do it without writing a 65 part case statement? Is there a way to write some simple code such as: Y = {S[i - 1:0], S[63:i]}; I tried…
Robert Cardona
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Verilog Always block using (*) symbol

I have a simple question regarding how to write an always block in a Verilog module. If I have the following inputs in my Verilog module: input [31:0] PCplus4 ; // Value of PC + 4 input [31:0] A; // Value A, i.e.…
all_by_grace
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