10

i have a verilog code in which there is a line as follows:

parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;

here what will be stored in RAM_DEPTH and what does the << operator do here.

Jubin Patel
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biren.K
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3 Answers3

23

<< is a binary shift, shifting 1 to the left 8 places.

4'b0001 << 1 => 4'b0010

>> is a binary right shift adding 0's to the MSB.
>>> is a signed shift which maintains the value of the MSB if the left input is signed.

4'sb1011 >>  1 => 0101
4'sb1011 >>> 1 => 1101

Three ways to indicate left operand is signed:

module shift;
  logic        [3:0] test1 = 4'b1000;
  logic signed [3:0] test2 = 4'b1000;

  initial begin
    $display("%b", $signed(test1) >>> 1 ); //Explicitly set as signed
    $display("%b", test2          >>> 1 ); //Declared as signed type
    $display("%b", 4'sb1000       >>> 1 ); //Signed constant
    $finish;
  end
endmodule
Morgan
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  • Thank you .. :) and also thanks for sharing the concept of '>>>' operator.. :) – biren.K Jul 17 '13 at 05:43
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    The >>> operator only preserves the MSB if the shifted operand is signed. If the shifted operand is unsigned, as in your example, the >>> operator inserts zeros just like the >> operator. –  Jul 17 '13 at 10:57
  • `$signed(test1) >>> 1` is not working for me. Xilinx ISE with ISim. – Yvon Oct 06 '14 at 06:24
  • @Yvon It should work, unless bug in Xilinx ISE, you could post a question with a code example your trying. otherwise try it out on [eda playground](http://www.edaplayground.com). – Morgan Oct 06 '14 at 14:33
  • @Morgan I pasted your second block of code into ISim, and it says `Syntax error near "signed".` and `logic is an unknown type`. It seems ISim does not recognize those keywords. – Yvon Oct 13 '14 at 21:06
  • @Morgan Oh I changed `logic` to `reg` then all of the three works, giving `1100`. – Yvon Oct 13 '14 at 21:07
  • @Yvon, those are System Verilog keywords, changing file extension to .sv often switches the compiler over. – Morgan Oct 14 '14 at 05:28
  • @Yvon Signed has been part of verilog for some time, if that is not supported sounds like your stuck with verilog 95 syntax. – Morgan Oct 14 '14 at 08:13
  • If it is register value do we need to assign to same variable – Chandan Choudhury Sep 12 '21 at 20:32
  • @ChandanChoudhury any variable can take the shifted value of another, just be careful with the word lengths. – Morgan Sep 14 '21 at 09:12
6

1 << ADDR_WIDTH means 1 will be shifted 8 bits to the left and will be assigned as the value for RAM_DEPTH.

In addition, 1 << ADDR_WIDTH also means 2^ADDR_WIDTH.

Given ADDR_WIDTH = 8, then 2^8 = 256 and that will be the value for RAM_DEPTH

e19293001
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3

<< is the left-shift operator, as it is in many other languages.

Here RAM_DEPTH will be 1 left-shifted by 8 bits, which is equivalent to 2^8, or 256.

dwikle
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