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Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

From Wikipedia:

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

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Handling parameterization in SystemVerilog packages

SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parameterized, so dealing with parameterized members is problematic. In practice…
JeffW
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<= Assignment Operator in Verilog

What does the <= do in Verilog? For example: always @(posedge Clock) begin if (Clear) begin BCD1 <= 0; BCD0 <= 0; end end
biw
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How to set all the bits to be 0 in a two-dimensional array in Verilog?

I've built a 8*2bits array to represent a piece of memory in Verilog reg [1:0] m [0:7] There is a reset signal for this memory and if reset is 1, all the bits in this memory should be reset to 0. But I don't know how to set all the bits of m in a…
Michael
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What's the best way to tell if a bus contains a single x in Verilog?

I have a test bench that monitors a bus. Some of the signals (bits) within the bus can be 1'bx. For a variety of reasons, I need to know if any of the signals within the bus are 1'bx. What's the best way to test (not for synthesis -- only for…
Doov
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Can we have an array of custom modules?

Can we have an array of instances for a custom module? For example: we can have input [15:0] a; - this creates a bus. Can we do same thing for custom modules, i.e. DFF [15:0] d;, where DFF is a custom module? Here I intend to create 16 instances of…
John
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is there a verilog tutorial where you build a very simple microprocessor?

I'm a programmer wishing to learn verilog. What would be amazingly neat would be a tutorial where one constructs a tiny microprocessor with a very clean design, something like an Intel 4004, and then goes on to actually make it using an fpga and…
John Lawrence Aspden
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Difference between @(posedge Clk); a<= 1'b1; and @(posedge Clk) a<= 1'b1;

Is there any difference between @(posedge Clk); a<= 1'b1; and @(posedge Clk) a<= 1'b1; Note the semicolon after Clk. I came across similar lines of code when I was browsing through a testbench. I did some simple experiments and I could not…
Pulimon
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Random number generation on Spartan-3E

I need to generate pseudo-random numbers for my genetic algorithm on a Spartan-3E FPGA and i want to implement it in verilog: could you give me any pointers on this?
akosch
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How to use const in verilog

Instead of using module ... ( .. ) ; #15 endmodule I want use module ... ( ... ) ; // GateDelay is a const, like in c language const int GateDelay = 15 ; # GateDelay endmodule Or same thing module ... ( ... ) ; // assume…
user478571
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Implementation of simple microprocessor using verilog

I am trying to make a simple microprocessor in verilog as a way to understand verilog and assembly at the same time. I am not sure if I am implementing what I think of microprocessors well enough or if I am completely wrong. Should I simplify the…
AdoobII
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Sharing constants across languages

I have a long list of constants that I need access to in several projects which are in different languages(Verilog, C, C++ and C#). Rather than repeating them in each language, is there a good way to share these? The only thing I could think of…
Kristin Morris
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Instantiate Modules in Generate For Loop in Verilog

I'm trying to instantiate some modules in Verilog using a generate block since I'm going to be instantiating a variable amount of them. genvar i; generate for (i=1; i<=10; i=i+1) begin status whatever_status ( .clk(clk), …
Colin
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Difference between Behavioral, RTL and gate Level

I'm trying to fully understand the differences between the abstraction levels of Verilog, I get what the description of each level says but I still can't get it on the play. For this case, I will paste some Verilog codes and what I think about…
lcjury
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How to use clock gating in RTL?

I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL? Example1: always_comb begin gated_clk = clk &…
newbie
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Best way to access the uvm_config_db from the testbench?

I want to create a clock in my top level testbench whose period can be controlled from the test. What I did was set the period into the uvm_config_db and get it back in the testbench. I had to put in a #1 to make sure that the build phase was…
nguthrie
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