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Can we have an array of instances for a custom module?

For example: we can have input [15:0] a; - this creates a bus. Can we do same thing for custom modules, i.e. DFF [15:0] d;, where DFF is a custom module? Here I intend to create 16 instances of the DFF module.

Qiu
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2 Answers2

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Verilog arrays of instances were added in Verilog-1995 (IEEE 1364-1995). They can be used with gates, user-defined primitives, and modules. Generates, which are more powerful but also more complex, were added in Verilog-2001.

Here is an example array of module instances:

DFF d[15:0] (clk, DFF_i, DFF_o);

For each port connection, if the size matches that of the formal parameter then it is connected to every instance. Otherwise each instance is connected to a part-select (or bit-select) of the expression.

mark4o
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  • Are these modules instantiated parallelly or one after other? – eldos Nov 01 '14 at 23:05
  • @eldos: If the size of a port connection matches that of the formal parameter then it is connected in parallel to every instance. Using a vector you can connect the instances in serial. – mark4o Nov 02 '14 at 13:00
  • @mark4o Do these kind of instantiations work properly as expected ? `DFF d[15:0] (clk, DFF[15:0], DFF[16:1]);` – eldos Nov 02 '14 at 15:01
  • @eldos: sure, except you'll need to use different names for the module and the vector – mark4o Nov 03 '14 at 00:54
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it is not possible to do this directly (update: now after mark4o's answer I know that there is a way), but what you can do is using the generate statement to create multiple instances of your custom module and hook them up to your signals. Should look something like this:

wire DFF_i[15:0];
wire DFF_o[15:0];

generate
  genvar i;
  for (i=0; i<15; i=i+1) begin : dff
    custom i_custom(
       .clk(clk)
      ,.input(DFF_i[i])
      ,.output(DFF_o[i])
      );
  end
endgenerate

Otherwise there are probably some possibility during synthesis to use the correct custom modules, but I'm not an expert there.

Cheers, Daniel

danielpoe
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