How to set all the bits to be 0 in a two-dimensional array in Verilog?

Question

I've built a 8*2bits array to represent a piece of memory in Verilog

reg [1:0] m [0:7]

There is a reset signal for this memory and if reset is 1, all the bits in this memory should be reset to 0. But I don't know how to set all the bits of m in a concise way, because if there are hundreds thousands of bits in the memory, the following way is obviously unfeasible.

always@(posedge clk or posedge reset)
begin
  if (reset) 
    begin
      m[0]<=2'b00;
      m[1]<=2'b00;
      m[2]<=2'b00;
      m[3]<=2'b00;        
      m[4]<=2'b00;
      m[5]<=2'b00;
      m[6]<=2'b00;
      m[7]<=2'b00;
    end
  else
    ....
end

Although the memory array you describe will be synthesizable, I'm not sure it is a good idea for "hundreds thousands" of bits. Does your target FPGA/ASIC have some kind of RAM macro cell that would be more efficient? — , Dec 04 '13 at 12:03
@JoeHass I just use "hundreds thousands of bits" as example. I'm working on a design targeting FPGA and that piece of memory contains 2*64 bits at most. But I'm quite curious about your point.What's the meaning of "RAM macro cell"? How could it be more efficient to use "RAM macro cell"? I don't have much experience in FPGA. I appreciate it if you can paraphrase about it. Thanks! — Michael, Dec 04 '13 at 20:25

toolic · Accepted Answer · 2023-03-17T15:16:54.573

9

Use a for loop:

  integer i;
  always@(posedge clk or posedge reset)
  begin
    if (reset) 
      begin
        for (i=0; i<8; i=i+1) m[i] <= 2'b00;
      end
    else
      ....
  end

This is described in the IEEE Std 1800-2012 (Section 12.7.1 The for-loop, for example).

edited Mar 17 '23 at 15:16

answered Dec 03 '13 at 16:54

toolic

57,801
17
75
117

score 9 · Answer 2 · edited Dec 04 '13 at 11:41

9

If you can use the current system verilog syntax, then this should work:

always_ff @(posedge clk or posedge reset)
begin
  if(reset) begin
    m <= '{default:2'b00};
  end
  else
    ...
end

See section 5.11 (Array Literals) of the 1800-2012 IEEE standard.

edited Dec 04 '13 at 11:41

Morgan

19,934
8
58
84

answered Dec 03 '13 at 17:25

nguthrie

2,615
6
26
43

Thanks, I know this syntax in system verilog. But this syntax is a feature added to the system verilog so it won't work in Verilog – Michael Dec 03 '13 at 21:12
1

Just curious, why can't you use SV? I ask since I have gotten push back in the past on using it for synthesis, but haven't heard a good argument for why. – nguthrie Dec 04 '13 at 04:07
@nguthrie some times a project is tied to using specific version of synthesis tools. It can be part of risk management for the company and not wasting time on every new release. Sometimes the versions people have tied them selves to are quite old. – Morgan Dec 04 '13 at 11:37
@nguthrie Thank you for your suggestion. I'm quite interested in SV but I need to learn it in order to use it. And I have experience using V, so I choose to use V to finish this work. I plan to learn SV recently because I've found SV is very useful in verification, maybe also in design. could you give me some recommendation of tutorials or books? Thanks a lot – Michael Dec 04 '13 at 20:29
2

@Michael Presentation about useful SV features for design: http://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_presentation.pdf and the IEEE standard is linked to in my answer – nguthrie Dec 04 '13 at 21:22

Russell · Answer 3 · 2013-12-03T17:45:18.193

1

This is actually the one place where for loops are meant to be used.

for (i=0; i<8; i++)
  begin
    m[i] <= 2'b00;
  end

edited Dec 03 '13 at 17:45

answered Dec 03 '13 at 16:57

Russell

3,384
4
31
45

4

Note that the `++` increment operator is only available in SystemVerilog. – Morgan Dec 04 '13 at 11:40

How to set all the bits to be 0 in a two-dimensional array in Verilog?

3 Answers3

Linked