Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

system-verilog system-verilog-assertions system-verilog-dpi uvm vpi icarus iverilog verilator

6035 questions

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Understanding the difference between overflow and carry flags

I am designing a 16 bit ALU in verilog based on an existing RISC ISA. The ISA says that the carry flag is set when the operation is unsigned, and overflow is set when the operation is signed. The interesting thing is that the ISA implements ADD and…

verilog cpu-architecture alu carryflag signed-overflow

asked Sep 09 '21 at 21:23

richbai90

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3 answers

Simple Verilog VPI module to open audio files

I would like to write a VPI/PLI interface which will open audio files (i.e. wav, aiff, etc) and present the data to Verilog simulator. I am using Icarus at the moment and wish to use libsndfile to handle input file formats and data type…

audio signal-processing verilog libsndfile icarus

asked Jun 16 '11 at 13:12

errordeveloper

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In verilog, Is there any difference between import package at compilation unit scope and module header?

In verilog, Is there any difference between import package at compilation unit scope(1) and module header(2)? 1) at compilation unit scope import mypkg::*; module my_module( port_declaration ... 2) at module header module my_module import…

import compilation package verilog

asked Sep 30 '19 at 09:40

Yunsung Mo

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1 answer

Verilog naming convention of \add_34/U1_1_6

Can somebody explain what this naming convention means in the Verilog line below? I don't know what this \add_34/.... part means? ADDHXL \add_34/U1_1_6 (.A(n1022),.B(\add_34/carry[6] ),.CO(\add_34/carry[7] ),.S(N11)); If I have a wire named…

syntax verilog naming-conventions

asked Jul 14 '19 at 17:11

VSB

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3 answers

How to restart a Verilog simulation in Modelsim

I'm trying to debug a Verilog module. I find it tedious to have to stop a simulation, modify code, and then go through the process of starting the simulation again. Is there an easier way?

debugging module verilog modelsim

asked Mar 10 '11 at 20:56

node ninja

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Cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

This code fails to compile and gives the error as in the title at the "if(overflow)" line. always @(posedge clk or negedge overflow) begin if(overflow) count_posedge = count_posedge + 1; else count_posedge = 0; end I've…

verilog

asked Sep 08 '18 at 06:02

namcao00

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1 answer

Why use functions in verilog when there is module

Part 1: I was always told to use functions in Verilog to avoid code duplication. But can't I do that with a module? If my understanding is correct, all functions can be re-written as modules in Verilog except that modules cannot be instantiated from…

verilog hdl hardware

asked Dec 23 '17 at 18:51

user3219492

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2 answers

Verilog (assign in always)

I came to know that we can use assign statements in procedural blocks(like in always), what will be the difference in using "assign" inside always block and outside it(in concern with synthesized circuit). I mean when it is absolutely necessary to…

verilog

asked Jun 26 '17 at 11:51

RIshabh yadav

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2 answers

how to initialize ram of multiple instance with different contents in quartus

I designed a RAM module, and I need multiple instances of this module each with a different memory initialization file. The Quartus manual says that Quartus supports the $readmemh() function to initialize RAM. So I added two parameters to this…

verilog fpga intel-fpga quartus

asked Apr 03 '17 at 02:44

paigu

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1 answer

Do I need an else statement in a sequential always block?

Now I'm tying to implement the clock gating as the below. but I can't understand why and how do I handle the De signal? module ClockGating( input wire rst_n, input wire clk, input wire De, input wire…

verilog

asked Feb 28 '17 at 07:52

grander3

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1 answer

Simplest way to generate Verilog code from Chisel code

What is the simplest way to generate Verilog code from existing Chisel code? Would i have to create my own build file? For example from a standalone scala file (AND.scala) like the following one.. import Chisel._ class AND extends Module { val…

scala build verilog chisel

asked Jan 23 '17 at 21:08

mtosch

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3 answers

Verilog to GDSII compiler (open-source)

May be this question a bit not for StackOverflow, but both compilers and Verilog (which can be considered as programming language) are related to this project. Where can I find a open-source (or downloadable and free-to-noncommercial-use) compiler…

compiler-construction verilog circuit vlsi

asked Nov 15 '10 at 00:35

osgx

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Cocotb VHDL need for FLI

I am currently setting up a Cocotb based verification environment. I just discovered that the example provided with Cocotb don't work in my case if using VHDL, because my simulator has no FLI (foreign language interface). I get the following…

vhdl verilog modelsim intel-fpga cocotb

asked Nov 09 '16 at 16:31

user1654361

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2 answers

Generic in verilog from a vhdl programmer

What's the equivalent of the generic in verilog? For example entity my_entity generic(a : integer); port(x : in std_logic; y out std_logic); end entity my_entity; What's the equivalent for generic? Also what's the equivalent for the if generate and…

syntax vhdl verilog

asked Jul 27 '16 at 20:51

user8469759

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Verilog signed multiplication: Multiplying numbers of different sizes?

For some reason I have been unable to find any definitive resources or stackoverflow questions answering this: Does verilog take care of input and output dimensions when multiplying signed numbers? To be specific, what happens if I multiply a…

verilog system-verilog

asked Jun 19 '16 at 15:47

sirblobfish

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