Do I need an else statement in a sequential always block?

Question

Now I'm tying to implement the clock gating as the below. but I can't understand why and how do I handle the De signal?

module ClockGating( 


           input wire rst_n,
           input wire clk,
           input wire De,  
           input wire InReg,

           output reg OutReg

   );

   always @( posedge clk or negedge rst_n )
     begin
     if ( !rst_n ) begin   
            OutReg <= 0;
     end
     else begin
        if ( De ) begin
               OutReg  <= InReg;
            end
        else
               OutReg  <= OutReg;
     end
   end

endmodule

but I want to know if I use without else statement then what happens? can I use without the else statement?

module ClockGating( 


           input wire rst_n,
           input wire clk,
           input wire De,  
           input wire InReg,

           output reg OutReg

   );

   always @( posedge clk or negedge rst_n )
     begin
     if ( !rst_n ) begin   
            OutReg <= 0;
     end
     else begin
        if ( De ) begin
               OutReg  <= InReg;
            end
      end

endmodule

Yes you can remove the `else` statement, and `OutReg` will retains it's value, because it is a `reg` — Karan Shah, Mar 01 '17 at 05:29

score 5 · Accepted Answer · answered Feb 28 '17 at 09:16

5

Yes, you can use without the else (because it will behave identically to the version with the else). Yes, you should use without the else (because otherwise you look like an amateur and nobody wants that!)

OutReg is a reg. A reg in Verilog is just like a variable in any software language; its value will be whatever value that was assigned to it last. In your circuit, you do not wish to change the value of OutReg if De is not 1'b1, therefore you do not need to assign any new value to OutReg in that case. Hence, you don't need the else.

answered Feb 28 '17 at 09:16

Matthew Taylor

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But I'm concerned that will be remained as a latch after synthesis. and we have to get rid out the latch, as I know. – grander3 Mar 03 '17 at 06:57
1

@grander3 I promise you won't get a latch. If this were combinational logic you would be right to worry. If you don't have _complete assignment_ in combinational logic then it could be the case that the output retains its value, which requires some kind of storage to implement in hardware, which is why your synthesiser infers a latch. But your code is sequential logic. Sequential logic has storage - the flip-flops - so complete assignment is not necessary and the synthesiser inferring storage (flip-flops not latches) is exactly what is supposed to happen. – Matthew Taylor Mar 03 '17 at 09:05

Do I need an else statement in a sequential always block?

1 Answers1