Verilog naming convention of \add_34/U1_1_6

Question

Can somebody explain what this naming convention means in the Verilog line below? I don't know what this \add_34/.... part means?

ADDHXL \add_34/U1_1_6  (.A(n1022),.B(\add_34/carry[6] ),.CO(\add_34/carry[7] ),.S(N11));

If I have a wire named \add_34/carry[6] in my definition, should I have \add_34/carry[1] up to \add_34/carry[5], or is it optional?

I asked this question since compiling a part of my code, I get this syntax error:

Syntax error at or near token 'wire'.

Here is the code snippet:

RandomDelay  R00001(clk,rst_n,2'b10,a34_carry_pri_delayed_7,\add_34/carry[7]);
wire N11_pri_delayed;

And here is module defintion:

module RandomDelay ( clk, reset_not, seed, input_signal, delayed_signal );
  input [1:0] seed;
  input clk, reset_not, input_signal;
  output delayed_signal;
....

score 5 · Answer 1 · edited Dec 20 '22 at 14:52

It is called an 'escaped identifier'.

When an identifier starts with a backslash, every character except white space is assumed to be part of the name. (Thus the standard identifier rules go out the window.)

Thus the identifier in your case is "\add_34/U1_1_6". Identifiers of that type are normally generate by a program.
Thus this is a valid identifier: \wow!/neverseen[]thissort@;of#++mess

Let's have a look at the identifier: \add_34/carry[6]. Note that the "[6]" is NOT an index! Is is seen as ASCII and part of the name.
The same again for \add_34/carry[7]. It also means somewhere there is a definition which goes:

wire \add_34/carry[6] ;
wire \add_34/carry[7] ;
// Note the space    ^ before the semicolon!

The other \add_34/carry[... variables may exist or not as we are all looking at individual wires here.

It is perfectly legal for there to be no \add_34/carry[5] or \add_34/carry[0]

Coming back to your code:

RandomDelay  R00001(clk,rst_n,2'b10,a34_carry_pri_delayed_7,\add_34/carry[7]);

You must thus place a space before the closing bracket:

RandomDelay  R00001(clk,rst_n,2'b10,a34_carry_pri_delayed_7,\add_34/carry[7] );
//                                                             ---->>> Here ^

Also should note that if the variable was declares `wire [7:6] add_34_carry;`, then `add_34_carry[5]` would not exist either, though it would be valid to read and write to it; reads yielding the default value `1'bx`, writes doing nothing. — Unn, Jul 15 '19 at 19:08

Verilog naming convention of \add_34/U1_1_6

1 Answers1