In verilog, Is there any difference between import package at compilation unit scope and module header?

Question

In verilog, Is there any difference between import package at compilation unit scope(1) and module header(2)?

1) at compilation unit scope

import mypkg::*;
module my_module(
  port_declaration
  ...

2) at module header

module my_module
import mypkg::*;
(
  port_declaration
  ...

There is no compile error for all above cases. I expected that, with 1) way, it might cause duplicated import warning or error when there was another file that import mypkg at its compilation unit scope, but there was not.

Any difference between them?

Answer 1

In verilog both will cause compilation errors, so no difference :-). In System Verilog there is a difference in scoping.

The import pkg::* before module declaration will pull all definitions of the package in the global scope. It means that all modules defined in this file, or in other files which follow your file on the command line will be aware of this import. For example:

 import pkg::abc_t;
 module top;
    abc_t a;
    ...
 endmodule
 module child;
    abc_t b;
    ...
 endmodule 

Import inside a module will only pull the package content into this module scope:

 module top;
    import pkg::abc_t;
    abc_t a;
    ...
 endmodule
 module child;
    abc_t b; << error, not visible, needs import first
    ...
 endmodule 

So far so good, but what if the module port uses the package? In the first case no problem:

  import pkg::*;
  module top(input abc_t abc);

But import in the global scope is usually a bad thing, which can cause issues in big projects. The solution is to use import in the module header.

module top
import pkg::*;
(input abc_t abc);

Now you have the package imported in the module scope and let port declarations see this import as well.