Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

system-verilog system-verilog-assertions system-verilog-dpi uvm vpi icarus iverilog verilator

6035 questions

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1 answer

How does SystemVerilog `force` work?

I have a hierarchy of modules where I am trying to do a force to get different value at different module interface. I am working on a component whose task is to inject transaction to a module down the hierarchy, bypassing the drives from the modules…

verilog system-verilog

asked Jun 12 '16 at 12:57

Gautam

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3 answers

urandom_range(), urandom(), random() in verilog

I am confused between these three functions and I was wondering for some explanation. If I set the range how do I make the range exclusive or inclusive? Are the ranges inclusive or exclusive if I don't specify the range?

random verilog

asked Apr 18 '16 at 15:17

Syed Rumman

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1 answer

Is it possible to take input port as array in verilog?

module median_five(out1,a[0],a[1],a[2],a[3],a[4],en,clka); input [7:0] a[0:4]; output out1; endmodule **It is giving error. module median_five(out1,a,b,c,d,e,en,clka); …

verilog

asked Apr 02 '16 at 07:24

B.R

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0 answers

SP605 Spartan 6 DDR3 addressing

the following post is quite long, but since I have had trouble making the SP605 board properly interact with the DDR3 for over a month now, hopefully this will be useful to others in the same situation as I find myself in. I am pretty certain it's a…

memory interface verilog xilinx spartan

asked Jan 06 '16 at 01:22

buped82

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1 answer

generating random numbers in verilog

I ran into this issue while writing a test bench for a project. I found how to use $random in verilog but for some reason it produces strange results for me. I have 2 16 bit regs called A and B, I tested it with random number between 0-10 every…

random verilog

asked Dec 01 '15 at 02:25

gps

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4 answers

Why does an If statement cause a latch in verilog?

I am trying to code a controller/data-path implementation in Verilog, and I am confused on what will cause an unwanted latch. Essentially, I have a state machine updating on the negedge clock. This state machine sends 5 control signals (loadSquare,…

verilog fpga xilinx

asked Nov 13 '15 at 02:56

Anthony

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2 answers

Using display in verilog

I am new to verilog and I understand it is not a sequential language. So, I wanted to ask is there some way to display results in a module after some execution?Because display should always be inside initial block and so there is no way I can use…

verilog

asked Nov 11 '15 at 14:51

user4685154

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2 answers

FSM export using Yosys

I am using Yosys to synthesize my Verilog designs. I want to export the FSM in my Verilog design using the Yosys command fsm_export, but it does not generate anything. I wonder how is this command supposed to be called. The series of commands I…

verilog fsm yosys

asked Sep 18 '15 at 07:13

adrianX

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2 answers

Does Verilog support short circuit evaluation?

If I have an if statement like: if(risingEdge && cnt == 3'b111) begin ... end Will it check on cnt if risingEdge is not true? Does this even matter inside of an HDL?

verilog

asked Jul 11 '10 at 20:38

samoz

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Format specifications for real numbers

I would like to print some real numbers to a log file. To make them easy to read I would like them to all have the same width. I know these numbers will range from 0 to 4095.75 so I tried this: $display("expected= %4.2f, actual= %4.2f", expected,…

verilog system-verilog

asked Apr 28 '15 at 17:23

nguthrie

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1 answer

Verify Parameters in Verilog

I have created a module which accepts a single parameter specifying the byte width of the module's data lines. It looks something like: module wrapper# ( parameter DATA_BYTE_WIDTH = 1 ) ( din, dout, .. ); localparam DATA_BIT_WIDTH =…

verilog hdl xilinx-ise

asked Apr 22 '15 at 16:23

Chris

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4 answers

Do all Flip Flops in a design need to be resettable (ASIC)?

I'm trying to understand clock-reset in a chip. In a design what criteria are used to decide whether a flop should be assigned to a value (typically to zero) during reset? always_ff @(posedge clk or negedge reset) begin : process_w_reset …

vhdl verilog system-verilog asic

asked Apr 11 '15 at 04:02

newbie

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2 answers

Passing a module name as parameter

I want to create this generic wrapper for a bunch of modules I am writing. The wrapper should provide the ability to connect these modules to different type of NoCs without having to change the behavior of the inner modules. I thought that one way…

hardware verilog system-verilog register-transfer-level

asked Apr 10 '15 at 20:57

igon

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verilog "~" operator in addition operation gives unwanted result

In the following simplified Verilog code: wire [31:0] depth; wire mode_u2 = 1'h0; assign depth = 'h80 + (~mode_u2); if I do a display on depth, and simulate it with VCS (2014.12-1) $display("depth is 0x%2x", depth); i'm getting 0x7f, instead of…

verilog system-verilog

asked Feb 20 '15 at 23:19

shakimura

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1 answer

Is there a way to get the name a Verilog module was instantiated with?

I'd like to do some simulation debugging in Verilog and want to add $display to some modules. However, I want to be able to track the output a single module provides. I'd like to be able to get the name that the current module was instantiated with…

verilog system-verilog

asked Jan 29 '15 at 21:26

oconnor0

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